| Message ID | 3cc3d14c-f98f-1aa9-4cd9-27af34746f99@epam.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi Artem, On 06/12/16 14:16, Artem Mygaiev wrote: > Fix macro for ARM Jazelle CPU feature identification: value of 0 indicates > that CPU does not support ARM Jazelle (PFR0[11:8]) NIT: The register is called ID_PFR0 not PFR0. > > Coverity-ID: 1381849 > > Signed-off-by: Artem Mygaiev <artem_mygaiev@epam.com> With that change: Reviewed-by: Julien Grall <julien.grall@arm.com> > > --- > xen/include/asm-arm/cpufeature.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/xen/include/asm-arm/cpufeature.h b/xen/include/asm-arm/cpufeature.h > index af60fe3..c0a25ae 100644 > --- a/xen/include/asm-arm/cpufeature.h > +++ b/xen/include/asm-arm/cpufeature.h > @@ -24,7 +24,7 @@ > #define cpu_has_arm (boot_cpu_feature32(arm) == 1) > #define cpu_has_thumb (boot_cpu_feature32(thumb) >= 1) > #define cpu_has_thumb2 (boot_cpu_feature32(thumb) >= 3) > -#define cpu_has_jazelle (boot_cpu_feature32(jazelle) >= 0) > +#define cpu_has_jazelle (boot_cpu_feature32(jazelle) > 0) > #define cpu_has_thumbee (boot_cpu_feature32(thumbee) == 1) > #define cpu_has_aarch32 (cpu_has_arm || cpu_has_thumb) > >
On Tue, 6 Dec 2016, Julien Grall wrote: > Hi Artem, > > On 06/12/16 14:16, Artem Mygaiev wrote: > > Fix macro for ARM Jazelle CPU feature identification: value of 0 indicates > > that CPU does not support ARM Jazelle (PFR0[11:8]) > > NIT: The register is called ID_PFR0 not PFR0. > > > > > Coverity-ID: 1381849 > > > > Signed-off-by: Artem Mygaiev <artem_mygaiev@epam.com> > > With that change: > > Reviewed-by: Julien Grall <julien.grall@arm.com> Fixed, and applied > > > > --- > > xen/include/asm-arm/cpufeature.h | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/xen/include/asm-arm/cpufeature.h > > b/xen/include/asm-arm/cpufeature.h > > index af60fe3..c0a25ae 100644 > > --- a/xen/include/asm-arm/cpufeature.h > > +++ b/xen/include/asm-arm/cpufeature.h > > @@ -24,7 +24,7 @@ > > #define cpu_has_arm (boot_cpu_feature32(arm) == 1) > > #define cpu_has_thumb (boot_cpu_feature32(thumb) >= 1) > > #define cpu_has_thumb2 (boot_cpu_feature32(thumb) >= 3) > > -#define cpu_has_jazelle (boot_cpu_feature32(jazelle) >= 0) > > +#define cpu_has_jazelle (boot_cpu_feature32(jazelle) > 0) > > #define cpu_has_thumbee (boot_cpu_feature32(thumbee) == 1) > > #define cpu_has_aarch32 (cpu_has_arm || cpu_has_thumb) > > > > > > -- > Julien Grall >
diff --git a/xen/include/asm-arm/cpufeature.h b/xen/include/asm-arm/cpufeature.h index af60fe3..c0a25ae 100644 --- a/xen/include/asm-arm/cpufeature.h +++ b/xen/include/asm-arm/cpufeature.h @@ -24,7 +24,7 @@ #define cpu_has_arm (boot_cpu_feature32(arm) == 1) #define cpu_has_thumb (boot_cpu_feature32(thumb) >= 1) #define cpu_has_thumb2 (boot_cpu_feature32(thumb) >= 3) -#define cpu_has_jazelle (boot_cpu_feature32(jazelle) >= 0) +#define cpu_has_jazelle (boot_cpu_feature32(jazelle) > 0) #define cpu_has_thumbee (boot_cpu_feature32(thumbee) == 1) #define cpu_has_aarch32 (cpu_has_arm || cpu_has_thumb)
Fix macro for ARM Jazelle CPU feature identification: value of 0 indicates that CPU does not support ARM Jazelle (PFR0[11:8]) Coverity-ID: 1381849 Signed-off-by: Artem Mygaiev <artem_mygaiev@epam.com> --- xen/include/asm-arm/cpufeature.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)