| Message ID | 1481538958-13588-1-git-send-email-luwei.kang@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
>>> On 12.12.16 at 11:35, <luwei.kang@intel.com> wrote: > If a counter happend overflow just clear corresponding bit of > IA32_PERF_GLOBAL_OVF_CTRL, rather than clear all the bit of this msr. The code change is fine, but the description appears to be wrong: Isn't the change to avoid bits getting wrongly set, rather than any getting wrongly cleared? Jan
> >>> On 12.12.16 at 11:35, <luwei.kang@intel.com> wrote: > > If a counter happend overflow just clear corresponding bit of > > IA32_PERF_GLOBAL_OVF_CTRL, rather than clear all the bit of this msr. > > The code change is fine, but the description appears to be wrong: > Isn't the change to avoid bits getting wrongly set, rather than any getting wrongly cleared? > just set the corresponding bits of which counter happened overflow, rather than set all the available bits of IA32_PERF_GLOBAL_OVF_CTRL when happened pmu interrupt. Or Remove the redundant bits set of IA32_PERF_GLOBAL_OVF_CTRL. Is that OK? Thank, Luwei Kang
>>> On 12.12.16 at 12:40, <luwei.kang@intel.com> wrote: >> >>> On 12.12.16 at 11:35, <luwei.kang@intel.com> wrote: >> > If a counter happend overflow just clear corresponding bit of >> > IA32_PERF_GLOBAL_OVF_CTRL, rather than clear all the bit of this msr. >> >> The code change is fine, but the description appears to be wrong: >> Isn't the change to avoid bits getting wrongly set, rather than any getting wrongly cleared? >> > just set the corresponding bits of which counter happened overflow, rather > than set all the available bits of IA32_PERF_GLOBAL_OVF_CTRL when happened > pmu interrupt. > Or > Remove the redundant bits set of IA32_PERF_GLOBAL_OVF_CTRL. The former seems better to me. Jan
diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c index e8049ed..613aafe 100644 --- a/xen/arch/x86/cpu/vpmu_intel.c +++ b/xen/arch/x86/cpu/vpmu_intel.c @@ -868,7 +868,7 @@ static int core2_vpmu_do_interrupt(struct cpu_user_regs *regs) if ( is_pmc_quirk ) handle_pmc_quirk(msr_content); core2_vpmu_cxt->global_status |= msr_content; - msr_content = ~global_ovf_ctrl_mask; + msr_content &= ~global_ovf_ctrl_mask; wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, msr_content); } else
If a counter happend overflow just clear corresponding bit of IA32_PERF_GLOBAL_OVF_CTRL, rather than clear all the bit of this msr. Signed-off-by: Luwei Kang <luwei.kang@intel.com> --- xen/arch/x86/cpu/vpmu_intel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)