| Message ID | 1482397663-98715-1-git-send-email-wangzhou1@hisilicon.com (mailing list archive) |
|---|---|
| State | New, archived |
| Delegated to: | Bjorn Helgaas |
| Headers | show |
On 2016/12/22 17:07, Zhou Wang wrote: > Multiple PCIe host bridges may exists in one PCIe segment. So bus range for each > host bridge should be in the coverage of bus range of related PCIe segment. > > This patch will support this kind of scenario: > > MCFG: > bus range: 0x00~0xff. > segment: 0. > DSDT: > host bridge 1: > bus range: 0x00~0x1f. > segment: 0. > host bridge 2: > bus range: 0x20~0x4f. > segment: 0. > > Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> > --- > drivers/acpi/pci_mcfg.c | 5 ++--- > 1 file changed, 2 insertions(+), 3 deletions(-) > > diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c > index b5b376e..46a3e32 100644 > --- a/drivers/acpi/pci_mcfg.c > +++ b/drivers/acpi/pci_mcfg.c > @@ -40,11 +40,10 @@ phys_addr_t pci_mcfg_lookup(u16 seg, struct resource *bus_res) > struct mcfg_entry *e; > > /* > - * We expect exact match, unless MCFG entry end bus covers more than > - * specified by caller. > + * We expect the range in bus_res in the coverage of MCFG bus range. > */ > list_for_each_entry(e, &pci_mcfg_list, list) { > - if (e->segment == seg && e->bus_start == bus_res->start && > + if (e->segment == seg && e->bus_start <= bus_res->start && > e->bus_end >= bus_res->end) > return e->addr; > } > Any idea about this RFC patch? Thanks, Zhou . -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 22.12.2016 10:07, Zhou Wang wrote: > Multiple PCIe host bridges may exists in one PCIe segment. So bus range for each > host bridge should be in the coverage of bus range of related PCIe segment. > > This patch will support this kind of scenario: > > MCFG: > bus range: 0x00~0xff. > segment: 0. > DSDT: > host bridge 1: > bus range: 0x00~0x1f. > segment: 0. > host bridge 2: > bus range: 0x20~0x4f. > segment: 0. > > Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> > --- > drivers/acpi/pci_mcfg.c | 5 ++--- > 1 file changed, 2 insertions(+), 3 deletions(-) > > diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c > index b5b376e..46a3e32 100644 > --- a/drivers/acpi/pci_mcfg.c > +++ b/drivers/acpi/pci_mcfg.c > @@ -40,11 +40,10 @@ phys_addr_t pci_mcfg_lookup(u16 seg, struct resource *bus_res) > struct mcfg_entry *e; > > /* > - * We expect exact match, unless MCFG entry end bus covers more than > - * specified by caller. > + * We expect the range in bus_res in the coverage of MCFG bus range. > */ > list_for_each_entry(e, &pci_mcfg_list, list) { > - if (e->segment == seg && e->bus_start == bus_res->start && > + if (e->segment == seg && e->bus_start <= bus_res->start && > e->bus_end >= bus_res->end) > return e->addr; > } > Looks good to me. Reviewed-by: Tomasz Nowicki <tn@semihalf.com> Thanks, Tomasz -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 2017/1/3 14:39, Tomasz Nowicki wrote: > On 22.12.2016 10:07, Zhou Wang wrote: >> Multiple PCIe host bridges may exists in one PCIe segment. So bus range for each >> host bridge should be in the coverage of bus range of related PCIe segment. >> >> This patch will support this kind of scenario: >> >> MCFG: >> bus range: 0x00~0xff. >> segment: 0. >> DSDT: >> host bridge 1: >> bus range: 0x00~0x1f. >> segment: 0. >> host bridge 2: >> bus range: 0x20~0x4f. >> segment: 0. >> >> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> >> --- >> drivers/acpi/pci_mcfg.c | 5 ++--- >> 1 file changed, 2 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c >> index b5b376e..46a3e32 100644 >> --- a/drivers/acpi/pci_mcfg.c >> +++ b/drivers/acpi/pci_mcfg.c >> @@ -40,11 +40,10 @@ phys_addr_t pci_mcfg_lookup(u16 seg, struct resource *bus_res) >> struct mcfg_entry *e; >> >> /* >> - * We expect exact match, unless MCFG entry end bus covers more than >> - * specified by caller. >> + * We expect the range in bus_res in the coverage of MCFG bus range. >> */ >> list_for_each_entry(e, &pci_mcfg_list, list) { >> - if (e->segment == seg && e->bus_start == bus_res->start && >> + if (e->segment == seg && e->bus_start <= bus_res->start && >> e->bus_end >= bus_res->end) >> return e->addr; >> } >> > > Looks good to me. > > Reviewed-by: Tomasz Nowicki <tn@semihalf.com> Hi Tomasz, Thanks for your review. Regards, Zhou > > Thanks, > Tomasz > > . > -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Thu, Dec 22, 2016 at 05:07:43PM +0800, Zhou Wang wrote: > Multiple PCIe host bridges may exists in one PCIe segment. So bus range for each > host bridge should be in the coverage of bus range of related PCIe segment. > > This patch will support this kind of scenario: > > MCFG: > bus range: 0x00~0xff. > segment: 0. > DSDT: > host bridge 1: > bus range: 0x00~0x1f. > segment: 0. > host bridge 2: > bus range: 0x20~0x4f. > segment: 0. "The configuration data provided by an MCFG region (ie PCI segment and bus range) may span multiple host bridges. Current code in pci_mcfg_lookup() carries out an exact match of host bridge bus range start value against the MCFG region(s) bus range start value which would cause configurations like the following: MCFG region: bus range: 0x00~0xff. segment: 0. PCI host bridges configuration (segment numbers and bus ranges): host bridge 1: bus range: 0x00~0x1f. segment: 0. host bridge 2: bus range: 0x20~0x4f. segment: 0. to fail, in that the bus range start value for host bridge 2 does not match the bus range start value of the respective MCFG region. Relax the bus range check in pci_mcfg_lookup() to cater for PCI configurations with multiple host bridges sharing the same MCFG region." Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> > Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> > --- > drivers/acpi/pci_mcfg.c | 5 ++--- > 1 file changed, 2 insertions(+), 3 deletions(-) > > diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c > index b5b376e..46a3e32 100644 > --- a/drivers/acpi/pci_mcfg.c > +++ b/drivers/acpi/pci_mcfg.c > @@ -40,11 +40,10 @@ phys_addr_t pci_mcfg_lookup(u16 seg, struct resource *bus_res) > struct mcfg_entry *e; > > /* > - * We expect exact match, unless MCFG entry end bus covers more than > - * specified by caller. > + * We expect the range in bus_res in the coverage of MCFG bus range. > */ > list_for_each_entry(e, &pci_mcfg_list, list) { > - if (e->segment == seg && e->bus_start == bus_res->start && > + if (e->segment == seg && e->bus_start <= bus_res->start && > e->bus_end >= bus_res->end) > return e->addr; > } > -- > 1.9.1 > -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 2017/1/3 20:00, Lorenzo Pieralisi wrote: > On Thu, Dec 22, 2016 at 05:07:43PM +0800, Zhou Wang wrote: >> Multiple PCIe host bridges may exists in one PCIe segment. So bus range for each >> host bridge should be in the coverage of bus range of related PCIe segment. >> >> This patch will support this kind of scenario: >> >> MCFG: >> bus range: 0x00~0xff. >> segment: 0. >> DSDT: >> host bridge 1: >> bus range: 0x00~0x1f. >> segment: 0. >> host bridge 2: >> bus range: 0x20~0x4f. >> segment: 0. > > "The configuration data provided by an MCFG region (ie PCI segment and > bus range) may span multiple host bridges. > > Current code in pci_mcfg_lookup() carries out an exact match of host > bridge bus range start value against the MCFG region(s) bus range start > value which would cause configurations like the following: > > MCFG region: > bus range: 0x00~0xff. > segment: 0. > > PCI host bridges configuration (segment numbers and bus ranges): > host bridge 1: > bus range: 0x00~0x1f. > segment: 0. > host bridge 2: > bus range: 0x20~0x4f. > segment: 0. > > to fail, in that the bus range start value for host bridge 2 does > not match the bus range start value of the respective MCFG region. > > Relax the bus range check in pci_mcfg_lookup() to cater for > PCI configurations with multiple host bridges sharing the same > MCFG region." > > Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Hi Lorenzo, Thanks for your view. I will modify the commit message and post a new version patch. Regards, Zhou > >> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> >> --- >> drivers/acpi/pci_mcfg.c | 5 ++--- >> 1 file changed, 2 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c >> index b5b376e..46a3e32 100644 >> --- a/drivers/acpi/pci_mcfg.c >> +++ b/drivers/acpi/pci_mcfg.c >> @@ -40,11 +40,10 @@ phys_addr_t pci_mcfg_lookup(u16 seg, struct resource *bus_res) >> struct mcfg_entry *e; >> >> /* >> - * We expect exact match, unless MCFG entry end bus covers more than >> - * specified by caller. >> + * We expect the range in bus_res in the coverage of MCFG bus range. >> */ >> list_for_each_entry(e, &pci_mcfg_list, list) { >> - if (e->segment == seg && e->bus_start == bus_res->start && >> + if (e->segment == seg && e->bus_start <= bus_res->start && >> e->bus_end >= bus_res->end) >> return e->addr; >> } >> -- >> 1.9.1 >> > > . > -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c index b5b376e..46a3e32 100644 --- a/drivers/acpi/pci_mcfg.c +++ b/drivers/acpi/pci_mcfg.c @@ -40,11 +40,10 @@ phys_addr_t pci_mcfg_lookup(u16 seg, struct resource *bus_res) struct mcfg_entry *e; /* - * We expect exact match, unless MCFG entry end bus covers more than - * specified by caller. + * We expect the range in bus_res in the coverage of MCFG bus range. */ list_for_each_entry(e, &pci_mcfg_list, list) { - if (e->segment == seg && e->bus_start == bus_res->start && + if (e->segment == seg && e->bus_start <= bus_res->start && e->bus_end >= bus_res->end) return e->addr; }
Multiple PCIe host bridges may exists in one PCIe segment. So bus range for each host bridge should be in the coverage of bus range of related PCIe segment. This patch will support this kind of scenario: MCFG: bus range: 0x00~0xff. segment: 0. DSDT: host bridge 1: bus range: 0x00~0x1f. segment: 0. host bridge 2: bus range: 0x20~0x4f. segment: 0. Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> --- drivers/acpi/pci_mcfg.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)