| Message ID | a4d90de597cfcfab5fddeeb538505774a980818b.1485180017.git-series.maxime.ripard@free-electrons.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, Jan 23, 2017 at 03:00:45PM +0100, Maxime Ripard wrote: > The ARM Mali Utgard GPU family is embedded into a number of SoCs from > Allwinner, Amlogic, Mediatek or Rockchip. > > Add a binding for the GPU of that family. > > Reviewed-by: Linus Walleij <linus.walleij@linaro.org> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> > > --- > > Changes from v1: > - Dropped the arm,mali-utgard compatible > - Made the clocks mandatory > - Added Linus Walleij Reviewed-by, and the ST compatible for the Mali > --- > Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 79 ++++++++- > 1 file changed, 79 insertions(+), 0 deletions(-) > create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt > > diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt > new file mode 100644 > index 000000000000..ba0edcdd1b00 > --- /dev/null > +++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt > @@ -0,0 +1,79 @@ > +ARM Mali Utgard GPU > +=================== > + > +Required properties: > + - compatible > + * Must be one of the following: > + + "arm,mali-300" > + + "arm,mali-400" > + + "arm,mali-450" > + * And, optionally, one of the vendor specific compatible: > + + allwinner,sun4i-a10-mali > + + allwinner,sun7i-a20-mali And stericsson,db8500-mali? > + > + - reg: Physical base address and length of the GPU registers > + > + - interrupts: an entry for each entry in interrupt-names. > + See ../interrupt-controller/interrupts.txt for details. > + > + - interrupt-names: > + * ppX: Pixel Processor X interrupt (X from 0 to 7) > + * ppmmuX: Pixel Processor X MMU interrupt (X from 0 to 7) > + * pp: Pixel Processor broadcast interrupt (mali-450 only) > + * gp: Geometry Processor interrupt > + * gpmmu: Geometry Processor MMU interrupt > + > + - clocks: an entry for each entry in clock-names > + - clock-names: > + * bus: bus clock for the GPU > + * core: clock driving the GPU itself assigned-clocks? > + > +Optional properties: > + - interrupt-names and interrupts: > + * pmu: Power Management Unit interrupt, if implemented in hardware > + > +Vendor-specific bindings > +------------------------ > + > +The Mali GPU is integrated very differently from one SoC to > +another. In order to accomodate those differences, you have the option > +to specify one more vendor-specific compatible, among: > + > + - allwinner,sun4i-a10-mali > + Required properties: > + * resets: phandle to the reset line for the GPU > + > + - allwinner,sun7i-a20-mali > + Required properties: > + * resets: phandle to the reset line for the GPU > + > + - stericsson,db8500-mali > + Required properties: > + * interrupt-names and interrupts: > + + combined: combined interrupt of all of the above lines > + > +Example: > + > +mali: gpu@01c40000 { Drop the leading 0. > + compatible = "allwinner,sun7i-a20-mali", "arm,mali-400"; > + reg = <0x01c40000 0x10000>; > + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "gp", > + "gpmmu", > + "pp0", > + "ppmmu0", > + "pp1", > + "ppmmu1", > + "pmu"; > + clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; > + clock-names = "bus", "core"; > + resets = <&ccu RST_BUS_GPU>; > +}; > + > + > > base-commit: 49def1853334396f948dcb4cedb9347abb318df5 > -- > git-series 0.8.11
Hi Rob, On Fri, Jan 27, 2017 at 02:19:13PM -0600, Rob Herring wrote: > On Mon, Jan 23, 2017 at 03:00:45PM +0100, Maxime Ripard wrote: > > The ARM Mali Utgard GPU family is embedded into a number of SoCs from > > Allwinner, Amlogic, Mediatek or Rockchip. > > > > Add a binding for the GPU of that family. > > > > Reviewed-by: Linus Walleij <linus.walleij@linaro.org> > > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> > > > > --- > > > > Changes from v1: > > - Dropped the arm,mali-utgard compatible > > - Made the clocks mandatory > > - Added Linus Walleij Reviewed-by, and the ST compatible for the Mali > > --- > > Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 79 ++++++++- > > 1 file changed, 79 insertions(+), 0 deletions(-) > > create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt > > > > diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt > > new file mode 100644 > > index 000000000000..ba0edcdd1b00 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt > > @@ -0,0 +1,79 @@ > > +ARM Mali Utgard GPU > > +=================== > > + > > +Required properties: > > + - compatible > > + * Must be one of the following: > > + + "arm,mali-300" > > + + "arm,mali-400" > > + + "arm,mali-450" > > + * And, optionally, one of the vendor specific compatible: > > + + allwinner,sun4i-a10-mali > > + + allwinner,sun7i-a20-mali > > And stericsson,db8500-mali? Good catch, I'll add it. > > + > > + - reg: Physical base address and length of the GPU registers > > + > > + - interrupts: an entry for each entry in interrupt-names. > > + See ../interrupt-controller/interrupts.txt for details. > > + > > + - interrupt-names: > > + * ppX: Pixel Processor X interrupt (X from 0 to 7) > > + * ppmmuX: Pixel Processor X MMU interrupt (X from 0 to 7) > > + * pp: Pixel Processor broadcast interrupt (mali-450 only) > > + * gp: Geometry Processor interrupt > > + * gpmmu: Geometry Processor MMU interrupt > > + > > + - clocks: an entry for each entry in clock-names > > + - clock-names: > > + * bus: bus clock for the GPU > > + * core: clock driving the GPU itself > > assigned-clocks? I didn't put it in there because it's optional, and was looking orthogonal to me, since it depends on the clock frequency out of reset and out of the bootloader running (and it's documented already as part of the generic clock bindings). Thanks, Maxime
On 01/30/2017 02:48 PM, Maxime Ripard wrote: > Hi Rob, > > On Fri, Jan 27, 2017 at 02:19:13PM -0600, Rob Herring wrote: >> On Mon, Jan 23, 2017 at 03:00:45PM +0100, Maxime Ripard wrote: >>> The ARM Mali Utgard GPU family is embedded into a number of SoCs from >>> Allwinner, Amlogic, Mediatek or Rockchip. >>> >>> Add a binding for the GPU of that family. >>> >>> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> >>> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> >>> >>> --- >>> >>> Changes from v1: >>> - Dropped the arm,mali-utgard compatible >>> - Made the clocks mandatory >>> - Added Linus Walleij Reviewed-by, and the ST compatible for the Mali >>> --- >>> Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 79 ++++++++- >>> 1 file changed, 79 insertions(+), 0 deletions(-) >>> create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt >>> >>> diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt >>> new file mode 100644 >>> index 000000000000..ba0edcdd1b00 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt >>> @@ -0,0 +1,79 @@ >>> +ARM Mali Utgard GPU >>> +=================== >>> + >>> +Required properties: >>> + - compatible >>> + * Must be one of the following: >>> + + "arm,mali-300" >>> + + "arm,mali-400" >>> + + "arm,mali-450" >>> + * And, optionally, one of the vendor specific compatible: >>> + + allwinner,sun4i-a10-mali >>> + + allwinner,sun7i-a20-mali >> >> And stericsson,db8500-mali? > > Good catch, I'll add it. I think you can safely add the following : amlogic,meson-gxbb-mali amlogic,meson-gxl-mali Neil
On Mon, Jan 30, 2017 at 05:24:06PM +0100, Neil Armstrong wrote: > >>> @@ -0,0 +1,79 @@ > >>> +ARM Mali Utgard GPU > >>> +=================== > >>> + > >>> +Required properties: > >>> + - compatible > >>> + * Must be one of the following: > >>> + + "arm,mali-300" > >>> + + "arm,mali-400" > >>> + + "arm,mali-450" > >>> + * And, optionally, one of the vendor specific compatible: > >>> + + allwinner,sun4i-a10-mali > >>> + + allwinner,sun7i-a20-mali > >> > >> And stericsson,db8500-mali? > > > > Good catch, I'll add it. > > I think you can safely add the following : > > amlogic,meson-gxbb-mali > amlogic,meson-gxl-mali Ack. Do you need any extra properties? Maxime
On 01/31/2017 10:56 AM, Maxime Ripard wrote: > On Mon, Jan 30, 2017 at 05:24:06PM +0100, Neil Armstrong wrote: >>>>> @@ -0,0 +1,79 @@ >>>>> +ARM Mali Utgard GPU >>>>> +=================== >>>>> + >>>>> +Required properties: >>>>> + - compatible >>>>> + * Must be one of the following: >>>>> + + "arm,mali-300" >>>>> + + "arm,mali-400" >>>>> + + "arm,mali-450" >>>>> + * And, optionally, one of the vendor specific compatible: >>>>> + + allwinner,sun4i-a10-mali >>>>> + + allwinner,sun7i-a20-mali >>>> >>>> And stericsson,db8500-mali? >>> >>> Good catch, I'll add it. >> >> I think you can safely add the following : >> >> amlogic,meson-gxbb-mali >> amlogic,meson-gxl-mali > > Ack. Do you need any extra properties? > > Maxime > Hi Maxime, No, it's ok with the generic properties, there is not reset lines for mali on Meson GX SoCs. Neil
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt new file mode 100644 index 000000000000..ba0edcdd1b00 --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt @@ -0,0 +1,79 @@ +ARM Mali Utgard GPU +=================== + +Required properties: + - compatible + * Must be one of the following: + + "arm,mali-300" + + "arm,mali-400" + + "arm,mali-450" + * And, optionally, one of the vendor specific compatible: + + allwinner,sun4i-a10-mali + + allwinner,sun7i-a20-mali + + - reg: Physical base address and length of the GPU registers + + - interrupts: an entry for each entry in interrupt-names. + See ../interrupt-controller/interrupts.txt for details. + + - interrupt-names: + * ppX: Pixel Processor X interrupt (X from 0 to 7) + * ppmmuX: Pixel Processor X MMU interrupt (X from 0 to 7) + * pp: Pixel Processor broadcast interrupt (mali-450 only) + * gp: Geometry Processor interrupt + * gpmmu: Geometry Processor MMU interrupt + + - clocks: an entry for each entry in clock-names + - clock-names: + * bus: bus clock for the GPU + * core: clock driving the GPU itself + +Optional properties: + - interrupt-names and interrupts: + * pmu: Power Management Unit interrupt, if implemented in hardware + +Vendor-specific bindings +------------------------ + +The Mali GPU is integrated very differently from one SoC to +another. In order to accomodate those differences, you have the option +to specify one more vendor-specific compatible, among: + + - allwinner,sun4i-a10-mali + Required properties: + * resets: phandle to the reset line for the GPU + + - allwinner,sun7i-a20-mali + Required properties: + * resets: phandle to the reset line for the GPU + + - stericsson,db8500-mali + Required properties: + * interrupt-names and interrupts: + + combined: combined interrupt of all of the above lines + +Example: + +mali: gpu@01c40000 { + compatible = "allwinner,sun7i-a20-mali", "arm,mali-400"; + reg = <0x01c40000 0x10000>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pmu"; + clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; + clock-names = "bus", "core"; + resets = <&ccu RST_BUS_GPU>; +}; + +