| Message ID | 1486377436-15380-1-git-send-email-zhi.a.wang@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, Feb 06, 2017 at 06:37:16PM +0800, Zhi Wang wrote: > execlist_update_context() will try to update PDPs in a context before a > ELSP submission only for full PPGTT mode, while PDPs was populated during > context initialization. Now the latter code path is removed. Let > execlist_update_context() also cover !FULL_PPGTT mode. > > Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> > Cc: Michal Winiarski <michal.winiarski@intel.com> > Cc: Michel Thierry <michel.thierry@intel.com> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> > Cc: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Zhenyu Wang <zhenyuw@linux.intel.com> > Cc: Zhiyuan Lv <zhiyuan.lv@intel.com> > Signed-off-by: Zhi Wang <zhi.a.wang@intel.com> My mistake from earlier missing the aliasing case. Fixes: 34869776c76b ("drm/i915: check ppgtt validity when init reg state") Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> -Chris
Thanks for the merging. I guess that with your patches of keeping PD structure under aliasing PPGTT mode in 32bit page table, the amount of PDPs will not change anymore under aliasing PPGTT mode. :P On 02/06/17 18:58, Chris Wilson wrote: > On Mon, Feb 06, 2017 at 06:37:16PM +0800, Zhi Wang wrote: >> execlist_update_context() will try to update PDPs in a context before a >> ELSP submission only for full PPGTT mode, while PDPs was populated during >> context initialization. Now the latter code path is removed. Let >> execlist_update_context() also cover !FULL_PPGTT mode. >> >> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> >> Cc: Michal Winiarski <michal.winiarski@intel.com> >> Cc: Michel Thierry <michel.thierry@intel.com> >> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> >> Cc: Chris Wilson <chris@chris-wilson.co.uk> >> Cc: Zhenyu Wang <zhenyuw@linux.intel.com> >> Cc: Zhiyuan Lv <zhiyuan.lv@intel.com> >> Signed-off-by: Zhi Wang <zhi.a.wang@intel.com> > > My mistake from earlier missing the aliasing case. > > Fixes: 34869776c76b ("drm/i915: check ppgtt validity when init reg state") > Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> > -Chris >
On Mon, Feb 06, 2017 at 07:03:39PM +0800, Zhi Wang wrote: > Thanks for the merging. I guess that with your patches of keeping PD > structure under aliasing PPGTT mode in 32bit page table, the amount > of PDPs will not change anymore under aliasing PPGTT mode. :P Yes. That's the idea atm, we will preallocate the aliasing table and then keep the tree intact. The only disadvantage with gen8+ aliasing mode (compared to gen6) will be that we still have to walk the va range to pin the tree so that when we call clear_range afterwards we don't reap. The benefit from my pov, is that the special case for aliasing_ppgtt is within the aliasing_ppgtt code and not in the common code (which should be optimised for full-ppgtt as that is the default/typical use). -Chris
On Mon, Feb 06, 2017 at 01:54:52PM -0000, Patchwork wrote: > == Series Details == > > Series: drm/i915: Let execlist_update_context() cover !FULL_PPGTT mode. > URL : https://patchwork.freedesktop.org/series/19155/ > State : success > > == Summary == > > Series 19155v1 drm/i915: Let execlist_update_context() cover !FULL_PPGTT mode. > https://patchwork.freedesktop.org/api/1.0/series/19155/revisions/1/mbox/ > > Test kms_force_connector_basic: > Subgroup force-load-detect: > dmesg-warn -> PASS (fi-snb-2520m) Thanks for the fix, pushed. -Chris
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 44a92ea..9084337 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -321,7 +321,8 @@ uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx, static u64 execlists_update_context(struct drm_i915_gem_request *rq) { struct intel_context *ce = &rq->ctx->engine[rq->engine->id]; - struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt; + struct i915_hw_ppgtt *ppgtt = + rq->ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt; u32 *reg_state = ce->lrc_reg_state; reg_state[CTX_RING_TAIL+1] = rq->tail;
execlist_update_context() will try to update PDPs in a context before a ELSP submission only for full PPGTT mode, while PDPs was populated during context initialization. Now the latter code path is removed. Let execlist_update_context() also cover !FULL_PPGTT mode. Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Michal Winiarski <michal.winiarski@intel.com> Cc: Michel Thierry <michel.thierry@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: Zhiyuan Lv <zhiyuan.lv@intel.com> Signed-off-by: Zhi Wang <zhi.a.wang@intel.com> --- drivers/gpu/drm/i915/intel_lrc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)