| Message ID | 1486704360-27361-3-git-send-email-sjitindarsingh@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Feb 10, 2017 at 04:25:52PM +1100, Suraj Jitindar Singh wrote: > The DPFD field in the LPCR is 3 bits wide. This has always been defined > as 0x3 << shift which indicates a 2 bit field, which is incorrect. > Correct this. > > Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Since this is a correct fix all on its own, I've applied it to ppc-for-2.9. > --- > target/ppc/cpu.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h > index bc2a2ce..bb96dd5 100644 > --- a/target/ppc/cpu.h > +++ b/target/ppc/cpu.h > @@ -381,7 +381,7 @@ struct ppc_slb_t { > #define LPCR_ISL (1ull << (63 - 2)) > #define LPCR_KBV (1ull << (63 - 3)) > #define LPCR_DPFD_SHIFT (63 - 11) > -#define LPCR_DPFD (0x3ull << LPCR_DPFD_SHIFT) > +#define LPCR_DPFD (0x7ull << LPCR_DPFD_SHIFT) > #define LPCR_VRMASD_SHIFT (63 - 16) > #define LPCR_VRMASD (0x1full << LPCR_VRMASD_SHIFT) > #define LPCR_RMLS_SHIFT (63 - 37)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index bc2a2ce..bb96dd5 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -381,7 +381,7 @@ struct ppc_slb_t { #define LPCR_ISL (1ull << (63 - 2)) #define LPCR_KBV (1ull << (63 - 3)) #define LPCR_DPFD_SHIFT (63 - 11) -#define LPCR_DPFD (0x3ull << LPCR_DPFD_SHIFT) +#define LPCR_DPFD (0x7ull << LPCR_DPFD_SHIFT) #define LPCR_VRMASD_SHIFT (63 - 16) #define LPCR_VRMASD (0x1full << LPCR_VRMASD_SHIFT) #define LPCR_RMLS_SHIFT (63 - 37)
The DPFD field in the LPCR is 3 bits wide. This has always been defined as 0x3 << shift which indicates a 2 bit field, which is incorrect. Correct this. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> --- target/ppc/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)