diff mbox

[v2,3/4] arm64: renesas: r8a7796 dtsi: Add all HSCIF nodes

Message ID 1481129088-22026-4-git-send-email-ulrich.hecht+renesas@gmail.com (mailing list archive)
State Accepted
Commit 8bc75621387afa3cbd4db73192edd99146b81334
Headers show

Commit Message

Ulrich Hecht Dec. 7, 2016, 4:44 p.m. UTC 
Add the device nodes for all HSCIF serial ports, incl. clocks, and
clock domain.

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 arch/arm64/boot/dts/renesas/r8a7796.dtsi | 70 ++++++++++++++++++++++++++++++++
 1 file changed, 70 insertions(+)

Comments

Sergei Shtylyov Dec. 8, 2016, 9:09 a.m. UTC | #1 
On 12/7/2016 7:44 PM, Ulrich Hecht wrote:

> Add the device nodes for all HSCIF serial ports, incl. clocks, and
> clock domain.

    Not power domain?

> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
>  arch/arm64/boot/dts/renesas/r8a7796.dtsi | 70 ++++++++++++++++++++++++++++++++
>  1 file changed, 70 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
> index 7bf0f2f..c508e0f 100644
> --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
> @@ -421,6 +421,76 @@
>  			};
>  		};
>
> +		hscif0: serial@e6540000 {
> +			compatible = "renesas,hscif-r8a7796",
> +				     "renesas,rcar-gen3-hscif",
> +				     "renesas,hscif";
> +			reg = <0 0xe6540000 0 96>;

    0xc0?

> +			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 520>,
> +				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
> +				 <&scif_clk>;
> +			clock-names = "fck", "brg_int", "scif_clk";
> +			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
> +			status = "disabled";
> +		};
> +
> +		hscif1: serial@e6550000 {
> +			compatible = "renesas,hscif-r8a7796",
> +				     "renesas,rcar-gen3-hscif",
> +				     "renesas,hscif";
> +			reg = <0 0xe6550000 0 96>;

    Here as well?

> +			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 519>,
> +				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
> +				 <&scif_clk>;
> +			clock-names = "fck", "brg_int", "scif_clk";
> +			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
> +			status = "disabled";
> +		};
> +
> +		hscif2: serial@e6560000 {
> +			compatible = "renesas,hscif-r8a7796",
> +				     "renesas,rcar-gen3-hscif",
> +				     "renesas,hscif";
> +			reg = <0 0xe6560000 0 96>;

    And here...

> +			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 518>,
> +				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
> +				 <&scif_clk>;
> +			clock-names = "fck", "brg_int", "scif_clk";
> +			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
> +			status = "disabled";
> +		};
> +
> +		hscif3: serial@e66a0000 {
> +			compatible = "renesas,hscif-r8a7796",
> +				     "renesas,rcar-gen3-hscif",
> +				     "renesas,hscif";
> +			reg = <0 0xe66a0000 0 96>;

    And here...

> +			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 517>,
> +				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
> +				 <&scif_clk>;
> +			clock-names = "fck", "brg_int", "scif_clk";
> +			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
> +			status = "disabled";
> +		};
> +
> +		hscif4: serial@e66b0000 {
> +			compatible = "renesas,hscif-r8a7796",
> +				     "renesas,rcar-gen3-hscif",
> +				     "renesas,hscif";
> +			reg = <0 0xe66b0000 0 96>;

    And here...

> +			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 516>,
> +				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
> +				 <&scif_clk>;
> +			clock-names = "fck", "brg_int", "scif_clk";
> +			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
> +			status = "disabled";
> +		};
> +
>  		scif2: serial@e6e88000 {
>  			compatible = "renesas,scif-r8a7796",
>  				     "renesas,rcar-gen3-scif", "renesas,scif";

MBR, Sergei
Simon Horman Feb. 13, 2017, 12:01 p.m. UTC | #2 
On Thu, Dec 08, 2016 at 12:09:02PM +0300, Sergei Shtylyov wrote:
> On 12/7/2016 7:44 PM, Ulrich Hecht wrote:
> 
> >Add the device nodes for all HSCIF serial ports, incl. clocks, and
> >clock domain.
> 
>    Not power domain?
> 
> >Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
> >Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> >---
> > arch/arm64/boot/dts/renesas/r8a7796.dtsi | 70 ++++++++++++++++++++++++++++++++
> > 1 file changed, 70 insertions(+)
> >
> >diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
> >index 7bf0f2f..c508e0f 100644
> >--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
> >+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
> >@@ -421,6 +421,76 @@
> > 			};
> > 		};
> >
> >+		hscif0: serial@e6540000 {
> >+			compatible = "renesas,hscif-r8a7796",
> >+				     "renesas,rcar-gen3-hscif",
> >+				     "renesas,hscif";
> >+			reg = <0 0xe6540000 0 96>;
> 
>    0xc0?

Do you mean 96 should be 0xc0 (= 192 = 2 * 96) ?

If so, perhaps the r8a7795 needs updating too?
Sergei Shtylyov Feb. 13, 2017, 12:06 p.m. UTC | #3 
Hello!

On 2/13/2017 3:01 PM, Simon Horman wrote:

>>> Add the device nodes for all HSCIF serial ports, incl. clocks, and
>>> clock domain.
>>
>>    Not power domain?
>>
>>> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
>>> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>>> ---
>>> arch/arm64/boot/dts/renesas/r8a7796.dtsi | 70 ++++++++++++++++++++++++++++++++
>>> 1 file changed, 70 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
>>> index 7bf0f2f..c508e0f 100644
>>> --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
>>> +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
>>> @@ -421,6 +421,76 @@
>>> 			};
>>> 		};
>>>
>>> +		hscif0: serial@e6540000 {
>>> +			compatible = "renesas,hscif-r8a7796",
>>> +				     "renesas,rcar-gen3-hscif",
>>> +				     "renesas,hscif";
>>> +			reg = <0 0xe6540000 0 96>;
>>
>>    0xc0?
>
> Do you mean 96 should be 0xc0 (= 192 = 2 * 96) ?

    Oops! 0x60, of course.

> If so, perhaps the r8a7795 needs updating too?

    Probably.

MBR, Sergei
Simon Horman Feb. 13, 2017, 1:03 p.m. UTC | #4 
On Mon, Feb 13, 2017 at 03:06:21PM +0300, Sergei Shtylyov wrote:
> Hello!
> 
> On 2/13/2017 3:01 PM, Simon Horman wrote:
> 
> >>>Add the device nodes for all HSCIF serial ports, incl. clocks, and
> >>>clock domain.
> >>
> >>   Not power domain?
> >>
> >>>Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
> >>>Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> >>>---
> >>>arch/arm64/boot/dts/renesas/r8a7796.dtsi | 70 ++++++++++++++++++++++++++++++++
> >>>1 file changed, 70 insertions(+)
> >>>
> >>>diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
> >>>index 7bf0f2f..c508e0f 100644
> >>>--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
> >>>+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
> >>>@@ -421,6 +421,76 @@
> >>>			};
> >>>		};
> >>>
> >>>+		hscif0: serial@e6540000 {
> >>>+			compatible = "renesas,hscif-r8a7796",
> >>>+				     "renesas,rcar-gen3-hscif",
> >>>+				     "renesas,hscif";
> >>>+			reg = <0 0xe6540000 0 96>;
> >>
> >>   0xc0?
> >
> >Do you mean 96 should be 0xc0 (= 192 = 2 * 96) ?
> 
>    Oops! 0x60, of course.

Thanks,

I queued up this patch after
- s/clock domain/power domain/ in changelog
- Updating to use 0x60 as you suggest above.

> >If so, perhaps the r8a7795 needs updating too?

Thanks, I'll see about sending an update.
diff mbox

Patch

diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 7bf0f2f..c508e0f 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -421,6 +421,76 @@ 
 			};
 		};
 
+		hscif0: serial@e6540000 {
+			compatible = "renesas,hscif-r8a7796",
+				     "renesas,rcar-gen3-hscif",
+				     "renesas,hscif";
+			reg = <0 0xe6540000 0 96>;
+			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 520>,
+				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			status = "disabled";
+		};
+
+		hscif1: serial@e6550000 {
+			compatible = "renesas,hscif-r8a7796",
+				     "renesas,rcar-gen3-hscif",
+				     "renesas,hscif";
+			reg = <0 0xe6550000 0 96>;
+			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 519>,
+				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			status = "disabled";
+		};
+
+		hscif2: serial@e6560000 {
+			compatible = "renesas,hscif-r8a7796",
+				     "renesas,rcar-gen3-hscif",
+				     "renesas,hscif";
+			reg = <0 0xe6560000 0 96>;
+			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 518>,
+				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			status = "disabled";
+		};
+
+		hscif3: serial@e66a0000 {
+			compatible = "renesas,hscif-r8a7796",
+				     "renesas,rcar-gen3-hscif",
+				     "renesas,hscif";
+			reg = <0 0xe66a0000 0 96>;
+			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 517>,
+				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			status = "disabled";
+		};
+
+		hscif4: serial@e66b0000 {
+			compatible = "renesas,hscif-r8a7796",
+				     "renesas,rcar-gen3-hscif",
+				     "renesas,hscif";
+			reg = <0 0xe66b0000 0 96>;
+			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 516>,
+				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
+				 <&scif_clk>;
+			clock-names = "fck", "brg_int", "scif_clk";
+			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+			status = "disabled";
+		};
+
 		scif2: serial@e6e88000 {
 			compatible = "renesas,scif-r8a7796",
 				     "renesas,rcar-gen3-scif", "renesas,scif";