| Message ID | 1486551058-22596-6-git-send-email-vidya.srinivas@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, 8 Feb 2017 16:20:54 +0530 Vidya Srinivas <vidya.srinivas@intel.com> wrote: > From: Uma Shankar <uma.shankar@intel.com> > > Fix the Sequence to program BXT DSI Latch and ULPS. > > Signed-off-by: Uma Shankar <uma.shankar@intel.com> > Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com> Reviewed-by: Bob Paauwe <bob.j.paauwe@intel.com> > --- > drivers/gpu/drm/i915/intel_dsi.c | 23 +++++------------------ > 1 file changed, 5 insertions(+), 18 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c > index c297ea9..538755b 100644 > --- a/drivers/gpu/drm/i915/intel_dsi.c > +++ b/drivers/gpu/drm/i915/intel_dsi.c > @@ -366,32 +366,19 @@ static void bxt_dsi_device_ready(struct intel_encoder *encoder) > > DRM_DEBUG_KMS("\n"); > > - /* Exit Low power state in 4 steps*/ > + /* Enable MIPI PHY transparent latch */ > for_each_dsi_port(port, intel_dsi->ports) { > - > - /* 1. Enable MIPI PHY transparent latch */ > val = I915_READ(BXT_MIPI_PORT_CTRL(port)); > I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD); > usleep_range(2000, 2500); > + } > > - /* 2. Enter ULPS */ > - val = I915_READ(MIPI_DEVICE_READY(port)); > - val &= ~ULPS_STATE_MASK; > - val |= (ULPS_STATE_ENTER | DEVICE_READY); > - I915_WRITE(MIPI_DEVICE_READY(port), val); > - /* at least 2us - relaxed for hrtimer subsystem optimization */ > - usleep_range(10, 50); > - > - /* 3. Exit ULPS */ > + /* Clear ULPS and set device ready */ > + for_each_dsi_port(port, intel_dsi->ports) { > val = I915_READ(MIPI_DEVICE_READY(port)); > val &= ~ULPS_STATE_MASK; > - val |= (ULPS_STATE_EXIT | DEVICE_READY); > I915_WRITE(MIPI_DEVICE_READY(port), val); > - usleep_range(1000, 1500); > - > - /* Clear ULPS and set device ready */ > - val = I915_READ(MIPI_DEVICE_READY(port)); > - val &= ~ULPS_STATE_MASK; > + usleep_range(2000, 2500); > val |= DEVICE_READY; > I915_WRITE(MIPI_DEVICE_READY(port), val); > }
On Wed, 15 Feb 2017, Bob Paauwe <bob.j.paauwe@intel.com> wrote: > On Wed, 8 Feb 2017 16:20:54 +0530 > Vidya Srinivas <vidya.srinivas@intel.com> wrote: > >> From: Uma Shankar <uma.shankar@intel.com> >> >> Fix the Sequence to program BXT DSI Latch and ULPS. >> >> Signed-off-by: Uma Shankar <uma.shankar@intel.com> >> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com> > > Reviewed-by: Bob Paauwe <bob.j.paauwe@intel.com> Pushed this one patch to dinq, thanks for the patch and review. BR, Jani. > >> --- >> drivers/gpu/drm/i915/intel_dsi.c | 23 +++++------------------ >> 1 file changed, 5 insertions(+), 18 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c >> index c297ea9..538755b 100644 >> --- a/drivers/gpu/drm/i915/intel_dsi.c >> +++ b/drivers/gpu/drm/i915/intel_dsi.c >> @@ -366,32 +366,19 @@ static void bxt_dsi_device_ready(struct intel_encoder *encoder) >> >> DRM_DEBUG_KMS("\n"); >> >> - /* Exit Low power state in 4 steps*/ >> + /* Enable MIPI PHY transparent latch */ >> for_each_dsi_port(port, intel_dsi->ports) { >> - >> - /* 1. Enable MIPI PHY transparent latch */ >> val = I915_READ(BXT_MIPI_PORT_CTRL(port)); >> I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD); >> usleep_range(2000, 2500); >> + } >> >> - /* 2. Enter ULPS */ >> - val = I915_READ(MIPI_DEVICE_READY(port)); >> - val &= ~ULPS_STATE_MASK; >> - val |= (ULPS_STATE_ENTER | DEVICE_READY); >> - I915_WRITE(MIPI_DEVICE_READY(port), val); >> - /* at least 2us - relaxed for hrtimer subsystem optimization */ >> - usleep_range(10, 50); >> - >> - /* 3. Exit ULPS */ >> + /* Clear ULPS and set device ready */ >> + for_each_dsi_port(port, intel_dsi->ports) { >> val = I915_READ(MIPI_DEVICE_READY(port)); >> val &= ~ULPS_STATE_MASK; >> - val |= (ULPS_STATE_EXIT | DEVICE_READY); >> I915_WRITE(MIPI_DEVICE_READY(port), val); >> - usleep_range(1000, 1500); >> - >> - /* Clear ULPS and set device ready */ >> - val = I915_READ(MIPI_DEVICE_READY(port)); >> - val &= ~ULPS_STATE_MASK; >> + usleep_range(2000, 2500); >> val |= DEVICE_READY; >> I915_WRITE(MIPI_DEVICE_READY(port), val); >> }
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index c297ea9..538755b 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -366,32 +366,19 @@ static void bxt_dsi_device_ready(struct intel_encoder *encoder) DRM_DEBUG_KMS("\n"); - /* Exit Low power state in 4 steps*/ + /* Enable MIPI PHY transparent latch */ for_each_dsi_port(port, intel_dsi->ports) { - - /* 1. Enable MIPI PHY transparent latch */ val = I915_READ(BXT_MIPI_PORT_CTRL(port)); I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD); usleep_range(2000, 2500); + } - /* 2. Enter ULPS */ - val = I915_READ(MIPI_DEVICE_READY(port)); - val &= ~ULPS_STATE_MASK; - val |= (ULPS_STATE_ENTER | DEVICE_READY); - I915_WRITE(MIPI_DEVICE_READY(port), val); - /* at least 2us - relaxed for hrtimer subsystem optimization */ - usleep_range(10, 50); - - /* 3. Exit ULPS */ + /* Clear ULPS and set device ready */ + for_each_dsi_port(port, intel_dsi->ports) { val = I915_READ(MIPI_DEVICE_READY(port)); val &= ~ULPS_STATE_MASK; - val |= (ULPS_STATE_EXIT | DEVICE_READY); I915_WRITE(MIPI_DEVICE_READY(port), val); - usleep_range(1000, 1500); - - /* Clear ULPS and set device ready */ - val = I915_READ(MIPI_DEVICE_READY(port)); - val &= ~ULPS_STATE_MASK; + usleep_range(2000, 2500); val |= DEVICE_READY; I915_WRITE(MIPI_DEVICE_READY(port), val); }