| Message ID | 1486920939-3661-1-git-send-email-ykaneko0929@gmail.com (mailing list archive) |
|---|---|
| State | Rejected |
| Headers | show |
Hi Kaneko-san, On Sun, Feb 12, 2017 at 6:35 PM, Yoshihiro Kaneko <ykaneko0929@gmail.com> wrote: > From: Takeshi Kihara <takeshi.kihara.df@renesas.com> > > This patch replaces PLL3 multiplication setting for DDR clock frequency. > > - After changes, new PLL3 multiplication setting: > MD19 MD17 : DDR clock frequency > ------------------------------- > 0 0 : DDR3200 > 0 1 : DDR2800 > 1 0 : DDR2400 > 1 1 : DDR1600 > > - Before changes, old PLL3 multiplication setting: > MD19 MD17 : DDR clock frequency > ------------------------------- > 0 0 : DDR3200 > 0 1 : DDR2133 > 1 0 : Prohibited setting > 1 1 : DDR1600 > > Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> > Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> JFTR, this patch, and its counterpart for r8a7796, are too experimental for upstream. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Geert-san, 2017-02-15 18:28 GMT+09:00 Geert Uytterhoeven <geert@linux-m68k.org>: > Hi Kaneko-san, > > On Sun, Feb 12, 2017 at 6:35 PM, Yoshihiro Kaneko <ykaneko0929@gmail.com> wrote: >> From: Takeshi Kihara <takeshi.kihara.df@renesas.com> >> >> This patch replaces PLL3 multiplication setting for DDR clock frequency. >> >> - After changes, new PLL3 multiplication setting: >> MD19 MD17 : DDR clock frequency >> ------------------------------- >> 0 0 : DDR3200 >> 0 1 : DDR2800 >> 1 0 : DDR2400 >> 1 1 : DDR1600 >> >> - Before changes, old PLL3 multiplication setting: >> MD19 MD17 : DDR clock frequency >> ------------------------------- >> 0 0 : DDR3200 >> 0 1 : DDR2133 >> 1 0 : Prohibited setting >> 1 1 : DDR1600 >> >> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> >> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> > > JFTR, this patch, and its counterpart for r8a7796, are too experimental > for upstream. Thanks for your review. I withdraw these patches. Thanks, Kaneko > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c index bfffdb0..9b34074 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c @@ -269,20 +269,20 @@ enum clk_ids { * 14 13 19 17 (MHz) *------------------------------------------------------------------- * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 - * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 - * 0 0 1 0 Prohibited setting + * 0 0 0 1 16.66 x 1 x180 x192 x144 x168 x144 + * 0 0 1 0 16.66 x 1 x180 x192 x144 x144 x144 * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 - * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 - * 0 1 1 0 Prohibited setting + * 0 1 0 1 20 x 1 x150 x160 x120 x140 x120 + * 0 1 1 0 20 x 1 x150 x160 x120 x120 x120 * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 - * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 - * 1 0 1 0 Prohibited setting + * 1 0 0 1 25 x 1 x120 x128 x96 x112 x96 + * 1 0 1 0 25 x 1 x120 x128 x96 x96 x96 * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 - * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 - * 1 1 1 0 Prohibited setting + * 1 1 0 1 33.33 / 2 x180 x192 x144 x168 x144 + * 1 1 1 0 33.33 / 2 x180 x192 x144 x144 x144 * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 */ #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ @@ -293,20 +293,20 @@ enum clk_ids { static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = { /* EXTAL div PLL1 mult PLL3 mult */ { 1, 192, 192, }, - { 1, 192, 128, }, - { 0, /* Prohibited setting */ }, + { 1, 192, 168, }, + { 1, 192, 144, }, { 1, 192, 192, }, { 1, 160, 160, }, - { 1, 160, 106, }, - { 0, /* Prohibited setting */ }, + { 1, 160, 140, }, + { 1, 160, 120, }, { 1, 160, 160, }, { 1, 128, 128, }, - { 1, 128, 84, }, - { 0, /* Prohibited setting */ }, + { 1, 128, 112, }, + { 1, 128, 96, }, { 1, 128, 128, }, { 2, 192, 192, }, - { 2, 192, 128, }, - { 0, /* Prohibited setting */ }, + { 2, 192, 168, }, + { 2, 192, 144, }, { 2, 192, 192, }, };