| Message ID | 20170210132959.16594-6-ander.conselvan.de.oliveira@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Feb 10, 2017 at 03:29:58PM +0200, Ander Conselvan de Oliveira wrote: > Geminilake's DDI IO power wells can only be enabled after a DPLL is > running and must be disabled before disabling the DPLL. Attempting to > change its state outside of this conditions will result in timeouts. > That is the case when intel_power_domains_sync_hw() is called from > intel_power_domains_init_hw(), where the attempt to disable the DDI IO > for an enabled port will timeout, so don't attempt to sync the hw state > for those power wells. > > Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> With my power well fixes patchset, this won't be needed, the existing sync_hw hook will be equivalent with the BIOS request reg sanitization added. > --- > drivers/gpu/drm/i915/intel_runtime_pm.c | 25 ++++++++++++++++++++++--- > 1 file changed, 22 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c > index b729a39..4d2dc31 100644 > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > @@ -2220,6 +2220,25 @@ static struct i915_power_well bxt_power_wells[] = { > }, > }; > > +static void noop_power_well_sync_hw(struct drm_i915_private *dev_priv, > + struct i915_power_well *power_well) > +{ > +} > + > +static const struct i915_power_well_ops glk_ddi_io_power_well_ops = { > + /* > + * DDI IO power wells in GLK can only be enabled after a DPLL is > + * running and must be disabled before disabling the DPLL. Any > + * attempt to change its state in different condidtions will lead > + * to timeouts. > + */ > + .sync_hw = noop_power_well_sync_hw, > + > + .enable = skl_power_well_enable, > + .disable = skl_power_well_disable, > + .is_enabled = skl_power_well_enabled, > +}; > + > static struct i915_power_well glk_power_wells[] = { > { > .name = "always-on", > @@ -2288,19 +2307,19 @@ static struct i915_power_well glk_power_wells[] = { > { > .name = "DDI A power well", > .domains = GLK_DISPLAY_DDI_A_POWER_DOMAINS, > - .ops = &skl_power_well_ops, > + .ops = &glk_ddi_io_power_well_ops, > .id = GLK_DISP_PW_DDI_A, > }, > { > .name = "DDI B power well", > .domains = GLK_DISPLAY_DDI_B_POWER_DOMAINS, > - .ops = &skl_power_well_ops, > + .ops = &glk_ddi_io_power_well_ops, > .id = SKL_DISP_PW_DDI_B, > }, > { > .name = "DDI C power well", > .domains = GLK_DISPLAY_DDI_C_POWER_DOMAINS, > - .ops = &skl_power_well_ops, > + .ops = &glk_ddi_io_power_well_ops, > .id = SKL_DISP_PW_DDI_C, > }, > }; > -- > 2.9.3 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index b729a39..4d2dc31 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -2220,6 +2220,25 @@ static struct i915_power_well bxt_power_wells[] = { }, }; +static void noop_power_well_sync_hw(struct drm_i915_private *dev_priv, + struct i915_power_well *power_well) +{ +} + +static const struct i915_power_well_ops glk_ddi_io_power_well_ops = { + /* + * DDI IO power wells in GLK can only be enabled after a DPLL is + * running and must be disabled before disabling the DPLL. Any + * attempt to change its state in different condidtions will lead + * to timeouts. + */ + .sync_hw = noop_power_well_sync_hw, + + .enable = skl_power_well_enable, + .disable = skl_power_well_disable, + .is_enabled = skl_power_well_enabled, +}; + static struct i915_power_well glk_power_wells[] = { { .name = "always-on", @@ -2288,19 +2307,19 @@ static struct i915_power_well glk_power_wells[] = { { .name = "DDI A power well", .domains = GLK_DISPLAY_DDI_A_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &glk_ddi_io_power_well_ops, .id = GLK_DISP_PW_DDI_A, }, { .name = "DDI B power well", .domains = GLK_DISPLAY_DDI_B_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &glk_ddi_io_power_well_ops, .id = SKL_DISP_PW_DDI_B, }, { .name = "DDI C power well", .domains = GLK_DISPLAY_DDI_C_POWER_DOMAINS, - .ops = &skl_power_well_ops, + .ops = &glk_ddi_io_power_well_ops, .id = SKL_DISP_PW_DDI_C, }, };
Geminilake's DDI IO power wells can only be enabled after a DPLL is running and must be disabled before disabling the DPLL. Attempting to change its state outside of this conditions will result in timeouts. That is the case when intel_power_domains_sync_hw() is called from intel_power_domains_init_hw(), where the attempt to disable the DDI IO for an enabled port will timeout, so don't attempt to sync the hw state for those power wells. Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> --- drivers/gpu/drm/i915/intel_runtime_pm.c | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-)