| Message ID | 1488902000-2658-22-git-send-email-thomas.petazzoni@free-electrons.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
From: Thomas Petazzoni > Sent: 07 March 2017 15:53 > On PPv2.2, the streaming mappings can be anywhere in the first 40 bits > of the physical address space. However, for the coherent mappings, we > still need them to be in the first 32 bits of the address space, > because all BM pools share a single register to store the high 32 bits > of the BM pool address, which means all BM pools must be allocated in > the same 4GB memory area. Are the coherent mappings just used for ring structures? If it might be reasonable to allocate them as a single entity, thus guaranteeing they all reside in a single 4G region. David
Hello, On Tue, 7 Mar 2017 17:24:21 +0000, David Laight wrote: > Are the coherent mappings just used for ring structures? > If it might be reasonable to allocate them as a single entity, > thus guaranteeing they all reside in a single 4G region. Do we have the guarantee that a DMA coherent allocation will not span a 4G boundary? Thanks, Thomas
From: Thomas Petazzoni > Sent: 07 March 2017 18:12 > Hello, > > On Tue, 7 Mar 2017 17:24:21 +0000, David Laight wrote: > > > Are the coherent mappings just used for ring structures? > > If it might be reasonable to allocate them as a single entity, > > thus guaranteeing they all reside in a single 4G region. > > Do we have the guarantee that a DMA coherent allocation will not span a > 4G boundary? I'm pretty sure they are guaranteed not to cross any boundary they don't have to. So a 16k buffer won't cross a 16k boundary. David
diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c index 0a3c470..92c47f3 100644 --- a/drivers/net/ethernet/marvell/mvpp2.c +++ b/drivers/net/ethernet/marvell/mvpp2.c @@ -6941,6 +6941,20 @@ static int mvpp2_probe(struct platform_device *pdev) /* Get system's tclk rate */ priv->tclk = clk_get_rate(priv->pp_clk); + if (priv->hw_version == MVPP22) { + err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(40)); + if (err) + goto err_mg_clk; + /* Sadly, the BM pools all share the same register to + * store the high 32 bits of their address. So they + * must all have the same high 32 bits, which forces + * us to restrict coherent memory to DMA_BIT_MASK(32). + */ + err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); + if (err) + goto err_mg_clk; + } + /* Initialize network controller */ err = mvpp2_init(pdev, priv); if (err < 0) {
On PPv2.2, the streaming mappings can be anywhere in the first 40 bits of the physical address space. However, for the coherent mappings, we still need them to be in the first 32 bits of the address space, because all BM pools share a single register to store the high 32 bits of the BM pool address, which means all BM pools must be allocated in the same 4GB memory area. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> --- drivers/net/ethernet/marvell/mvpp2.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+)