| Message ID | 1488931972-2865-2-git-send-email-dhinakaran.pandiyan@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Em Ter, 2017-03-07 às 16:12 -0800, Dhinakaran Pandiyan escreveu: > According to BSpec, "The CD clock frequency must be at least twice > the > frequency of the Azalia BCLK." and BCLK is configured to 96 MHz by > default. This check is needed because BXT and GLK support cdclk > frequencies less than 192 MHz. > > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > --- > drivers/gpu/drm/i915/intel_cdclk.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c > b/drivers/gpu/drm/i915/intel_cdclk.c > index e8c1181..7b1ac1d 100644 > --- a/drivers/gpu/drm/i915/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/intel_cdclk.c > @@ -1458,6 +1458,18 @@ static int > bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state, > pixel_rate = max(432000, pixel_rate); > } > > + /* According to BSpec, "The CD clock frequency must be at > least twice > + * the frequency of the Azalia BCLK." and BCLK is 96 MHz by > default. > + * The check for GLK has to be adjusted as the platform can > output > + * two pixels per clock. > + */ > + if (crtc_state->has_audio) { > + if (IS_GEMINILAKE(dev_priv)) > + pixel_rate = max(2 * 2 * 96000, pixel_rate); > + if (IS_BROXTON(dev_priv)) SKL also documents this in the page that explains the cdclk freq change sequences. The funny thing is that the minimum CDCLK for SKL seems to be 308.57, so that's still bigger than 96*2... Anyway, having this for completeness would probably be good, just in case I'm missing some detail that's important here. I'd like to see the SKL addition, but I can live without it in case you have some better argument, so if you don't send a new version, here's it: Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Perhaps it would also be interesting to have some sort of macro to identify the platform(s) that need the magic *2 calculation. A more confusion-proof version of this function would look like this: if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) if (HAS_2_PIXELS_PER_CLOCK(dev_priv)) pixel_rate = max(2 * 2 * 96000, pixel_rate); else pixel_rate = max(2 * 96000, pixel_rate); Maybe we'd be able to use the macro in other places too (I haven't checked). The new macro would definitely be part of a separate patch on top of these. > + pixel_rate = max(2 * 96000, pixel_rate); > + } > + > return pixel_rate; > } >
On Tue, 2017-03-14 at 17:47 -0300, Paulo Zanoni wrote: > Em Ter, 2017-03-07 às 16:12 -0800, Dhinakaran Pandiyan escreveu: > > According to BSpec, "The CD clock frequency must be at least twice > > the > > frequency of the Azalia BCLK." and BCLK is configured to 96 MHz by > > default. This check is needed because BXT and GLK support cdclk > > frequencies less than 192 MHz. > > > > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > --- > > drivers/gpu/drm/i915/intel_cdclk.c | 12 ++++++++++++ > > 1 file changed, 12 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c > > b/drivers/gpu/drm/i915/intel_cdclk.c > > index e8c1181..7b1ac1d 100644 > > --- a/drivers/gpu/drm/i915/intel_cdclk.c > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c > > @@ -1458,6 +1458,18 @@ static int > > bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state, > > pixel_rate = max(432000, pixel_rate); > > } > > > > + /* According to BSpec, "The CD clock frequency must be at > > least twice > > + * the frequency of the Azalia BCLK." and BCLK is 96 MHz by > > default. > > + * The check for GLK has to be adjusted as the platform can > > output > > + * two pixels per clock. > > + */ > > + if (crtc_state->has_audio) { > > + if (IS_GEMINILAKE(dev_priv)) > > + pixel_rate = max(2 * 2 * 96000, pixel_rate); > > + if (IS_BROXTON(dev_priv)) > > SKL also documents this in the page that explains the cdclk freq change > sequences. The funny thing is that the minimum CDCLK for SKL seems to > be 308.57, so that's still bigger than 96*2... Anyway, having this for > completeness would probably be good, just in case I'm missing some > detail that's important here. > > I'd like to see the SKL addition, but I can live without it in case you > have some better argument, so if you don't send a new version, here's > it: > > Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > > I did not include SKL as the lowest cdclk freq. it supports was higher than 2 * 96MHz. But, I agree it's good to include it for clarity. I'll send another version. > Perhaps it would also be interesting to have some sort of macro to > identify the platform(s) that need the magic *2 calculation. A more > confusion-proof version of this function would look like this: > > if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) > if (HAS_2_PIXELS_PER_CLOCK(dev_priv)) > pixel_rate = max(2 * 2 * 96000, pixel_rate); > else > pixel_rate = max(2 * 96000, pixel_rate); > > Maybe we'd be able to use the macro in other places too (I haven't > checked). The new macro would definitely be part of a separate patch on > top of these. > > > Agreed. Using a macro makes it cleaner, will send a patch for this too. -DK > > + pixel_rate = max(2 * 96000, pixel_rate); > > + } > > + > > return pixel_rate; > > } > > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Tue, 14 Mar 2017, "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com> wrote: > On Tue, 2017-03-14 at 17:47 -0300, Paulo Zanoni wrote: >> Em Ter, 2017-03-07 às 16:12 -0800, Dhinakaran Pandiyan escreveu: >> > According to BSpec, "The CD clock frequency must be at least twice >> > the >> > frequency of the Azalia BCLK." and BCLK is configured to 96 MHz by >> > default. This check is needed because BXT and GLK support cdclk >> > frequencies less than 192 MHz. >> > >> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> >> > --- >> > drivers/gpu/drm/i915/intel_cdclk.c | 12 ++++++++++++ >> > 1 file changed, 12 insertions(+) >> > >> > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c >> > b/drivers/gpu/drm/i915/intel_cdclk.c >> > index e8c1181..7b1ac1d 100644 >> > --- a/drivers/gpu/drm/i915/intel_cdclk.c >> > +++ b/drivers/gpu/drm/i915/intel_cdclk.c >> > @@ -1458,6 +1458,18 @@ static int >> > bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state, >> > pixel_rate = max(432000, pixel_rate); >> > } >> > >> > + /* According to BSpec, "The CD clock frequency must be at >> > least twice >> > + * the frequency of the Azalia BCLK." and BCLK is 96 MHz by >> > default. >> > + * The check for GLK has to be adjusted as the platform can >> > output >> > + * two pixels per clock. >> > + */ >> > + if (crtc_state->has_audio) { >> > + if (IS_GEMINILAKE(dev_priv)) >> > + pixel_rate = max(2 * 2 * 96000, pixel_rate); >> > + if (IS_BROXTON(dev_priv)) >> >> SKL also documents this in the page that explains the cdclk freq change >> sequences. The funny thing is that the minimum CDCLK for SKL seems to >> be 308.57, so that's still bigger than 96*2... Anyway, having this for >> completeness would probably be good, just in case I'm missing some >> detail that's important here. >> >> I'd like to see the SKL addition, but I can live without it in case you >> have some better argument, so if you don't send a new version, here's >> it: >> >> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> >> >> > > I did not include SKL as the lowest cdclk freq. it supports was higher > than 2 * 96MHz. But, I agree it's good to include it for clarity. I'll > send another version. > > >> Perhaps it would also be interesting to have some sort of macro to >> identify the platform(s) that need the magic *2 calculation. A more >> confusion-proof version of this function would look like this: >> >> if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) >> if (HAS_2_PIXELS_PER_CLOCK(dev_priv)) I didn't check the spec (where's the fun in that?!) about the terminology it uses, but isn't that just double data rate, or DDR? BR, Jani. >> pixel_rate = max(2 * 2 * 96000, pixel_rate); >> else >> pixel_rate = max(2 * 96000, pixel_rate); >> >> Maybe we'd be able to use the macro in other places too (I haven't >> checked). The new macro would definitely be part of a separate patch on >> top of these. >> >> >> > > Agreed. Using a macro makes it cleaner, will send a patch for this too. > > -DK > >> > + pixel_rate = max(2 * 96000, pixel_rate); >> > + } >> > + >> > return pixel_rate; >> > } >> > >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Wed, 2017-03-15 at 11:32 +0200, Jani Nikula wrote: > On Tue, 14 Mar 2017, "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com> wrote: > > On Tue, 2017-03-14 at 17:47 -0300, Paulo Zanoni wrote: > >> Em Ter, 2017-03-07 às 16:12 -0800, Dhinakaran Pandiyan escreveu: > >> > According to BSpec, "The CD clock frequency must be at least twice > >> > the > >> > frequency of the Azalia BCLK." and BCLK is configured to 96 MHz by > >> > default. This check is needed because BXT and GLK support cdclk > >> > frequencies less than 192 MHz. > >> > > >> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > >> > --- > >> > drivers/gpu/drm/i915/intel_cdclk.c | 12 ++++++++++++ > >> > 1 file changed, 12 insertions(+) > >> > > >> > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c > >> > b/drivers/gpu/drm/i915/intel_cdclk.c > >> > index e8c1181..7b1ac1d 100644 > >> > --- a/drivers/gpu/drm/i915/intel_cdclk.c > >> > +++ b/drivers/gpu/drm/i915/intel_cdclk.c > >> > @@ -1458,6 +1458,18 @@ static int > >> > bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state, > >> > pixel_rate = max(432000, pixel_rate); > >> > } > >> > > >> > + /* According to BSpec, "The CD clock frequency must be at > >> > least twice > >> > + * the frequency of the Azalia BCLK." and BCLK is 96 MHz by > >> > default. > >> > + * The check for GLK has to be adjusted as the platform can > >> > output > >> > + * two pixels per clock. > >> > + */ > >> > + if (crtc_state->has_audio) { > >> > + if (IS_GEMINILAKE(dev_priv)) > >> > + pixel_rate = max(2 * 2 * 96000, pixel_rate); > >> > + if (IS_BROXTON(dev_priv)) > >> > >> SKL also documents this in the page that explains the cdclk freq change > >> sequences. The funny thing is that the minimum CDCLK for SKL seems to > >> be 308.57, so that's still bigger than 96*2... Anyway, having this for > >> completeness would probably be good, just in case I'm missing some > >> detail that's important here. > >> > >> I'd like to see the SKL addition, but I can live without it in case you > >> have some better argument, so if you don't send a new version, here's > >> it: > >> > >> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > >> > >> > > > > I did not include SKL as the lowest cdclk freq. it supports was higher > > than 2 * 96MHz. But, I agree it's good to include it for clarity. I'll > > send another version. > > > > > >> Perhaps it would also be interesting to have some sort of macro to > >> identify the platform(s) that need the magic *2 calculation. A more > >> confusion-proof version of this function would look like this: > >> > >> if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) > >> if (HAS_2_PIXELS_PER_CLOCK(dev_priv)) > > I didn't check the spec (where's the fun in that?!) about the > terminology it uses, but isn't that just double data rate, or DDR? > > BR, > Jani. > > I found no reference to "DDR" in the spec., which thankfully avoids confusing this with the memory technology. -DK > >> pixel_rate = max(2 * 2 * 96000, pixel_rate); > >> else > >> pixel_rate = max(2 * 96000, pixel_rate); > >> > >> Maybe we'd be able to use the macro in other places too (I haven't > >> checked). The new macro would definitely be part of a separate patch on > >> top of these. > >> > >> > >> > > > > Agreed. Using a macro makes it cleaner, will send a patch for this too. > > > > -DK > > > >> > + pixel_rate = max(2 * 96000, pixel_rate); > >> > + } > >> > + > >> > return pixel_rate; > >> > } > >> > > >> _______________________________________________ > >> Intel-gfx mailing list > >> Intel-gfx@lists.freedesktop.org > >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx >
On Wed, Mar 15, 2017 at 06:03:58PM +0000, Pandiyan, Dhinakaran wrote: > On Wed, 2017-03-15 at 11:32 +0200, Jani Nikula wrote: > > On Tue, 14 Mar 2017, "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com> wrote: > > > On Tue, 2017-03-14 at 17:47 -0300, Paulo Zanoni wrote: > > >> Em Ter, 2017-03-07 às 16:12 -0800, Dhinakaran Pandiyan escreveu: > > >> > According to BSpec, "The CD clock frequency must be at least twice > > >> > the > > >> > frequency of the Azalia BCLK." and BCLK is configured to 96 MHz by > > >> > default. This check is needed because BXT and GLK support cdclk > > >> > frequencies less than 192 MHz. > > >> > > > >> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > >> > --- > > >> > drivers/gpu/drm/i915/intel_cdclk.c | 12 ++++++++++++ > > >> > 1 file changed, 12 insertions(+) > > >> > > > >> > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c > > >> > b/drivers/gpu/drm/i915/intel_cdclk.c > > >> > index e8c1181..7b1ac1d 100644 > > >> > --- a/drivers/gpu/drm/i915/intel_cdclk.c > > >> > +++ b/drivers/gpu/drm/i915/intel_cdclk.c > > >> > @@ -1458,6 +1458,18 @@ static int > > >> > bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state, > > >> > pixel_rate = max(432000, pixel_rate); > > >> > } > > >> > > > >> > + /* According to BSpec, "The CD clock frequency must be at > > >> > least twice > > >> > + * the frequency of the Azalia BCLK." and BCLK is 96 MHz by > > >> > default. > > >> > + * The check for GLK has to be adjusted as the platform can > > >> > output > > >> > + * two pixels per clock. > > >> > + */ > > >> > + if (crtc_state->has_audio) { > > >> > + if (IS_GEMINILAKE(dev_priv)) > > >> > + pixel_rate = max(2 * 2 * 96000, pixel_rate); > > >> > + if (IS_BROXTON(dev_priv)) > > >> > > >> SKL also documents this in the page that explains the cdclk freq change > > >> sequences. The funny thing is that the minimum CDCLK for SKL seems to > > >> be 308.57, so that's still bigger than 96*2... Anyway, having this for > > >> completeness would probably be good, just in case I'm missing some > > >> detail that's important here. > > >> > > >> I'd like to see the SKL addition, but I can live without it in case you > > >> have some better argument, so if you don't send a new version, here's > > >> it: > > >> > > >> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > > >> > > >> > > > > > > I did not include SKL as the lowest cdclk freq. it supports was higher > > > than 2 * 96MHz. But, I agree it's good to include it for clarity. I'll > > > send another version. > > > > > > > > >> Perhaps it would also be interesting to have some sort of macro to > > >> identify the platform(s) that need the magic *2 calculation. A more > > >> confusion-proof version of this function would look like this: > > >> > > >> if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) > > >> if (HAS_2_PIXELS_PER_CLOCK(dev_priv)) > > > > I didn't check the spec (where's the fun in that?!) about the > > terminology it uses, but isn't that just double data rate, or DDR? > > > > BR, > > Jani. > > > > > > I found no reference to "DDR" in the spec., which thankfully avoids > confusing this with the memory technology. What this was called back in the gen2/3 days is "double wide pipe". We could perhaps just keep using that name. Although the gen2/3 thing was something you could enable/disable on demand.
Em Qua, 2017-03-15 às 20:16 +0200, Ville Syrjälä escreveu: > On Wed, Mar 15, 2017 at 06:03:58PM +0000, Pandiyan, Dhinakaran wrote: > > > > On Wed, 2017-03-15 at 11:32 +0200, Jani Nikula wrote: > > > > > > On Tue, 14 Mar 2017, "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@ > > > intel.com> wrote: > > > > > > > > On Tue, 2017-03-14 at 17:47 -0300, Paulo Zanoni wrote: > > > > > > > > > > Em Ter, 2017-03-07 às 16:12 -0800, Dhinakaran Pandiyan > > > > > escreveu: > > > > > > > > > > > > According to BSpec, "The CD clock frequency must be at > > > > > > least twice > > > > > > the > > > > > > frequency of the Azalia BCLK." and BCLK is configured to 96 > > > > > > MHz by > > > > > > default. This check is needed because BXT and GLK support > > > > > > cdclk > > > > > > frequencies less than 192 MHz. > > > > > > > > > > > > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@int > > > > > > el.com> > > > > > > --- > > > > > > drivers/gpu/drm/i915/intel_cdclk.c | 12 ++++++++++++ > > > > > > 1 file changed, 12 insertions(+) > > > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c > > > > > > b/drivers/gpu/drm/i915/intel_cdclk.c > > > > > > index e8c1181..7b1ac1d 100644 > > > > > > --- a/drivers/gpu/drm/i915/intel_cdclk.c > > > > > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c > > > > > > @@ -1458,6 +1458,18 @@ static int > > > > > > bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state > > > > > > *crtc_state, > > > > > > pixel_rate = max(432000, > > > > > > pixel_rate); > > > > > > } > > > > > > > > > > > > + /* According to BSpec, "The CD clock frequency > > > > > > must be at > > > > > > least twice > > > > > > + * the frequency of the Azalia BCLK." and BCLK is > > > > > > 96 MHz by > > > > > > default. > > > > > > + * The check for GLK has to be adjusted as the > > > > > > platform can > > > > > > output > > > > > > + * two pixels per clock. > > > > > > + */ > > > > > > + if (crtc_state->has_audio) { > > > > > > + if (IS_GEMINILAKE(dev_priv)) > > > > > > + pixel_rate = max(2 * 2 * 96000, > > > > > > pixel_rate); > > > > > > + if (IS_BROXTON(dev_priv)) > > > > > > > > > > SKL also documents this in the page that explains the cdclk > > > > > freq change > > > > > sequences. The funny thing is that the minimum CDCLK for SKL > > > > > seems to > > > > > be 308.57, so that's still bigger than 96*2... Anyway, having > > > > > this for > > > > > completeness would probably be good, just in case I'm missing > > > > > some > > > > > detail that's important here. > > > > > > > > > > I'd like to see the SKL addition, but I can live without it > > > > > in case you > > > > > have some better argument, so if you don't send a new > > > > > version, here's > > > > > it: > > > > > > > > > > Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > > > > > > > > > > > > > > > > > > I did not include SKL as the lowest cdclk freq. it supports was > > > > higher > > > > than 2 * 96MHz. But, I agree it's good to include it for > > > > clarity. I'll > > > > send another version. > > > > > > > > > > > > > > > > > > Perhaps it would also be interesting to have some sort of > > > > > macro to > > > > > identify the platform(s) that need the magic *2 calculation. > > > > > A more > > > > > confusion-proof version of this function would look like > > > > > this: > > > > > > > > > > if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) > > > > > if (HAS_2_PIXELS_PER_CLOCK(dev_priv)) > > > > > > I didn't check the spec (where's the fun in that?!) about the > > > terminology it uses, but isn't that just double data rate, or > > > DDR? > > > > > > BR, > > > Jani. > > > > > > > > > > I found no reference to "DDR" in the spec., which thankfully avoids > > confusing this with the memory technology. > > What this was called back in the gen2/3 days is "double wide pipe". > We > could perhaps just keep using that name. Although the gen2/3 thing > was > something you could enable/disable on demand. At least in the docs I can find, this feature for the new platform is always referred to as "two pixels per clock". AFAIR the gen 2/3 thing is indeed "double wide" and I don't think it makes sense to call the new thing "double wide", even if it were the exact same thing. IMHO naming a feature of Gen 9 after something that's only present in Gen 2/3, even if it's the same, only adds confusion to the driver: now you're requiring that people working on new stuff actually have knowledge about the super old stuff for basically zero reason. You can just use the new name in the new context... This is the same reason why I'm not a big fan of using older #defines for registers that changed name but are still mostly the same on newer platforms: it requires that people reading the code actually know about all the different platforms, while having an additional #define wouldn't really hurt. But, anyway, that's just MHO. >
On Wed, Mar 15, 2017 at 03:39:58PM -0300, Paulo Zanoni wrote: > Em Qua, 2017-03-15 às 20:16 +0200, Ville Syrjälä escreveu: > > On Wed, Mar 15, 2017 at 06:03:58PM +0000, Pandiyan, Dhinakaran wrote: > > > > > > On Wed, 2017-03-15 at 11:32 +0200, Jani Nikula wrote: > > > > > > > > On Tue, 14 Mar 2017, "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@ > > > > intel.com> wrote: > > > > > > > > > > On Tue, 2017-03-14 at 17:47 -0300, Paulo Zanoni wrote: > > > > > > > > > > > > Em Ter, 2017-03-07 às 16:12 -0800, Dhinakaran Pandiyan > > > > > > escreveu: > > > > > > > > > > > > > > According to BSpec, "The CD clock frequency must be at > > > > > > > least twice > > > > > > > the > > > > > > > frequency of the Azalia BCLK." and BCLK is configured to 96 > > > > > > > MHz by > > > > > > > default. This check is needed because BXT and GLK support > > > > > > > cdclk > > > > > > > frequencies less than 192 MHz. > > > > > > > > > > > > > > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@int > > > > > > > el.com> > > > > > > > --- > > > > > > > drivers/gpu/drm/i915/intel_cdclk.c | 12 ++++++++++++ > > > > > > > 1 file changed, 12 insertions(+) > > > > > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c > > > > > > > b/drivers/gpu/drm/i915/intel_cdclk.c > > > > > > > index e8c1181..7b1ac1d 100644 > > > > > > > --- a/drivers/gpu/drm/i915/intel_cdclk.c > > > > > > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c > > > > > > > @@ -1458,6 +1458,18 @@ static int > > > > > > > bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state > > > > > > > *crtc_state, > > > > > > > pixel_rate = max(432000, > > > > > > > pixel_rate); > > > > > > > } > > > > > > > > > > > > > > + /* According to BSpec, "The CD clock frequency > > > > > > > must be at > > > > > > > least twice > > > > > > > + * the frequency of the Azalia BCLK." and BCLK is > > > > > > > 96 MHz by > > > > > > > default. > > > > > > > + * The check for GLK has to be adjusted as the > > > > > > > platform can > > > > > > > output > > > > > > > + * two pixels per clock. > > > > > > > + */ > > > > > > > + if (crtc_state->has_audio) { > > > > > > > + if (IS_GEMINILAKE(dev_priv)) > > > > > > > + pixel_rate = max(2 * 2 * 96000, > > > > > > > pixel_rate); > > > > > > > + if (IS_BROXTON(dev_priv)) > > > > > > > > > > > > SKL also documents this in the page that explains the cdclk > > > > > > freq change > > > > > > sequences. The funny thing is that the minimum CDCLK for SKL > > > > > > seems to > > > > > > be 308.57, so that's still bigger than 96*2... Anyway, having > > > > > > this for > > > > > > completeness would probably be good, just in case I'm missing > > > > > > some > > > > > > detail that's important here. > > > > > > > > > > > > I'd like to see the SKL addition, but I can live without it > > > > > > in case you > > > > > > have some better argument, so if you don't send a new > > > > > > version, here's > > > > > > it: > > > > > > > > > > > > Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > > > > > > > > > > > > > > > > > > > > > > I did not include SKL as the lowest cdclk freq. it supports was > > > > > higher > > > > > than 2 * 96MHz. But, I agree it's good to include it for > > > > > clarity. I'll > > > > > send another version. > > > > > > > > > > > > > > > > > > > > > > Perhaps it would also be interesting to have some sort of > > > > > > macro to > > > > > > identify the platform(s) that need the magic *2 calculation. > > > > > > A more > > > > > > confusion-proof version of this function would look like > > > > > > this: > > > > > > > > > > > > if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) > > > > > > if (HAS_2_PIXELS_PER_CLOCK(dev_priv)) > > > > > > > > I didn't check the spec (where's the fun in that?!) about the > > > > terminology it uses, but isn't that just double data rate, or > > > > DDR? > > > > > > > > BR, > > > > Jani. > > > > > > > > > > > > > > I found no reference to "DDR" in the spec., which thankfully avoids > > > confusing this with the memory technology. > > > > What this was called back in the gen2/3 days is "double wide pipe". > > We > > could perhaps just keep using that name. Although the gen2/3 thing > > was > > something you could enable/disable on demand. > > At least in the docs I can find, this feature for the new platform is > always referred to as "two pixels per clock". AFAIR the gen 2/3 thing > is indeed "double wide" and I don't think it makes sense to call the > new thing "double wide", even if it were the exact same thing. IMHO > naming a feature of Gen 9 after something that's only present in Gen > 2/3, even if it's the same, only adds confusion to the driver: now > you're requiring that people working on new stuff actually have > knowledge about the super old stuff for basically zero reason. You can > just use the new name in the new context... Dunno. I'll keep calling it double wide most likely. One less name for me to remember ;) > > This is the same reason why I'm not a big fan of using older #defines > for registers that changed name but are still mostly the same on newer > platforms: it requires that people reading the code actually know about > all the different platforms, while having an additional #define > wouldn't really hurt. But, anyway, that's just MHO. We'd have to duplicate boatloads of code if we wanted to match the bspec register names all the time (+ I have a feeling they keep renaming them even after the silicon has shipped). And duplicated code just means more bugs which are also harder to find since it reduces the testing coverage for each copy of the same code. Thus we really want to be using the old register names at least when the code as a whole can be shared. And I think sometimes using the old name and sometimes the new name would lead to even more confusion. I think there are a few cases where that is probably happening already, and people might not even realize because they no longer associate the old name with the new platform since most other parts of the code are using the new name. So I still think trying to follow the latest and greatest naming scheme of the day would just lead to chaos. IMO the best way to fix this would be to convinve the hardware folks to stop renaming things all the time.
On Tue, Mar 07, 2017 at 04:12:52PM -0800, Dhinakaran Pandiyan wrote: > According to BSpec, "The CD clock frequency must be at least twice the > frequency of the Azalia BCLK." and BCLK is configured to 96 MHz by > default. This check is needed because BXT and GLK support cdclk > frequencies less than 192 MHz. > > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > --- > drivers/gpu/drm/i915/intel_cdclk.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c > index e8c1181..7b1ac1d 100644 > --- a/drivers/gpu/drm/i915/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/intel_cdclk.c > @@ -1458,6 +1458,18 @@ static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state, > pixel_rate = max(432000, pixel_rate); > } > > + /* According to BSpec, "The CD clock frequency must be at least twice > + * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default. > + * The check for GLK has to be adjusted as the platform can output > + * two pixels per clock. > + */ > + if (crtc_state->has_audio) { > + if (IS_GEMINILAKE(dev_priv)) > + pixel_rate = max(2 * 2 * 96000, pixel_rate); BTW that x2 factor for GLK looks wrong. It should be /2. https://bugs.freedesktop.org/show_bug.cgi?id=100439 > + if (IS_BROXTON(dev_priv)) > + pixel_rate = max(2 * 96000, pixel_rate); > + } > + > return pixel_rate; > } > > -- > 2.7.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Wed, 2017-03-29 at 11:50 +0300, Ville Syrjälä wrote: > On Tue, Mar 07, 2017 at 04:12:52PM -0800, Dhinakaran Pandiyan wrote: > > According to BSpec, "The CD clock frequency must be at least twice the > > frequency of the Azalia BCLK." and BCLK is configured to 96 MHz by > > default. This check is needed because BXT and GLK support cdclk > > frequencies less than 192 MHz. > > > > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > --- > > drivers/gpu/drm/i915/intel_cdclk.c | 12 ++++++++++++ > > 1 file changed, 12 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c > > index e8c1181..7b1ac1d 100644 > > --- a/drivers/gpu/drm/i915/intel_cdclk.c > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c > > @@ -1458,6 +1458,18 @@ static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state, > > pixel_rate = max(432000, pixel_rate); > > } > > > > + /* According to BSpec, "The CD clock frequency must be at least twice > > + * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default. > > + * The check for GLK has to be adjusted as the platform can output > > + * two pixels per clock. > > + */ > > + if (crtc_state->has_audio) { > > + if (IS_GEMINILAKE(dev_priv)) > > + pixel_rate = max(2 * 2 * 96000, pixel_rate); > > BTW that x2 factor for GLK looks wrong. It should be /2. > > https://bugs.freedesktop.org/show_bug.cgi?id=100439 > BSpec[1] says cdclk needs to be > 2*96 MHz (azalia bclk). To set a cdclk > 192 MHz on GLK, we need to pass in max_pixclk = 2*192 MHz. But with a factor of /2, we can end up picking 158.4 MHz or 79.2 MHz for cdclk, which are lower than 192 MHz. static int glk_calc_cdclk(int max_pixclk) { if (max_pixclk > 2 * 158400) return 316800; else if (max_pixclk > 2 * 79200) return 158400; else return 79200; } [1] Geminilake Clocks "158.4 MHz CD (cannot be used when audio is enabled and Azalia BCLK is 96 MHz) 316.8 MHz CD 79.2 MHz CD (exclusively for resolutions up to 1080p in low power single pipe eDP/MIPI configurations, no audio support)" -DK > > + if (IS_BROXTON(dev_priv)) > > + pixel_rate = max(2 * 96000, pixel_rate); > > + } > > + > > return pixel_rate; > > } > > > > -- > > 2.7.4 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx >
On Wed, Mar 29, 2017 at 09:16:36PM +0000, Pandiyan, Dhinakaran wrote: > On Wed, 2017-03-29 at 11:50 +0300, Ville Syrjälä wrote: > > On Tue, Mar 07, 2017 at 04:12:52PM -0800, Dhinakaran Pandiyan wrote: > > > According to BSpec, "The CD clock frequency must be at least twice the > > > frequency of the Azalia BCLK." and BCLK is configured to 96 MHz by > > > default. This check is needed because BXT and GLK support cdclk > > > frequencies less than 192 MHz. > > > > > > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > > --- > > > drivers/gpu/drm/i915/intel_cdclk.c | 12 ++++++++++++ > > > 1 file changed, 12 insertions(+) > > > > > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c > > > index e8c1181..7b1ac1d 100644 > > > --- a/drivers/gpu/drm/i915/intel_cdclk.c > > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c > > > @@ -1458,6 +1458,18 @@ static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state, > > > pixel_rate = max(432000, pixel_rate); > > > } > > > > > > + /* According to BSpec, "The CD clock frequency must be at least twice > > > + * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default. > > > + * The check for GLK has to be adjusted as the platform can output > > > + * two pixels per clock. > > > + */ > > > + if (crtc_state->has_audio) { > > > + if (IS_GEMINILAKE(dev_priv)) > > > + pixel_rate = max(2 * 2 * 96000, pixel_rate); > > > > BTW that x2 factor for GLK looks wrong. It should be /2. > > > > https://bugs.freedesktop.org/show_bug.cgi?id=100439 > > > > BSpec[1] says cdclk needs to be > 2*96 MHz (azalia bclk). To set a cdclk > > 192 MHz on GLK, we need to pass in max_pixclk = 2*192 MHz. But with a > factor of /2, we can end up picking 158.4 MHz or 79.2 MHz for cdclk, > which are lower than 192 MHz. > > > static int glk_calc_cdclk(int max_pixclk) > { > if (max_pixclk > 2 * 158400) > return 316800; > else if (max_pixclk > 2 * 79200) > return 158400; > else > return 79200; > } > > [1] Geminilake Clocks > "158.4 MHz CD (cannot be used when audio is enabled and Azalia BCLK is > 96 MHz) > 316.8 MHz CD > 79.2 MHz CD (exclusively for resolutions up to 1080p in low power single > pipe eDP/MIPI configurations, no audio support)" Argh. So it's really about the cdclk freq vs. bclk. Apparently the fact that the pipe can output two pixels per clock doesn't extend to the HDA side. OK, then the code looks correct. But how do we know the bclk is really 96Mhz? Or are we just making a worst case estimate here? Base on the hda spec I think bclk should typically be 24 MHz, but of course the hda spec is so old that it probably has little to do with today's realities. I guess ideally we'd like the audio driver to tell us what the frequency is, or we'd dig that up from somewhere ourselves. Hmm. AUD_FREQ_CNTRL seems to have something. 96 vs. 48 MHz. But I'm not sure we could trust that at boot time. Not sure if the audio driver will make its own choice if BCLK somewhere. Can any alsa folks help us? > > > > -DK > > > > + if (IS_BROXTON(dev_priv)) > > > + pixel_rate = max(2 * 96000, pixel_rate); > > > + } > > > + > > > return pixel_rate; > > > } > > > > > > -- > > > 2.7.4 > > > > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx@lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > >
On Thu, 30 Mar 2017 13:42:09 +0200, Ville Syrjälä wrote: > > On Wed, Mar 29, 2017 at 09:16:36PM +0000, Pandiyan, Dhinakaran wrote: > > On Wed, 2017-03-29 at 11:50 +0300, Ville Syrjälä wrote: > > > On Tue, Mar 07, 2017 at 04:12:52PM -0800, Dhinakaran Pandiyan wrote: > > > > According to BSpec, "The CD clock frequency must be at least twice the > > > > frequency of the Azalia BCLK." and BCLK is configured to 96 MHz by > > > > default. This check is needed because BXT and GLK support cdclk > > > > frequencies less than 192 MHz. > > > > > > > > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > > > --- > > > > drivers/gpu/drm/i915/intel_cdclk.c | 12 ++++++++++++ > > > > 1 file changed, 12 insertions(+) > > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c > > > > index e8c1181..7b1ac1d 100644 > > > > --- a/drivers/gpu/drm/i915/intel_cdclk.c > > > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c > > > > @@ -1458,6 +1458,18 @@ static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state, > > > > pixel_rate = max(432000, pixel_rate); > > > > } > > > > > > > > + /* According to BSpec, "The CD clock frequency must be at least twice > > > > + * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default. > > > > + * The check for GLK has to be adjusted as the platform can output > > > > + * two pixels per clock. > > > > + */ > > > > + if (crtc_state->has_audio) { > > > > + if (IS_GEMINILAKE(dev_priv)) > > > > + pixel_rate = max(2 * 2 * 96000, pixel_rate); > > > > > > BTW that x2 factor for GLK looks wrong. It should be /2. > > > > > > https://bugs.freedesktop.org/show_bug.cgi?id=100439 > > > > > > > BSpec[1] says cdclk needs to be > 2*96 MHz (azalia bclk). To set a cdclk > > > 192 MHz on GLK, we need to pass in max_pixclk = 2*192 MHz. But with a > > factor of /2, we can end up picking 158.4 MHz or 79.2 MHz for cdclk, > > which are lower than 192 MHz. > > > > > > static int glk_calc_cdclk(int max_pixclk) > > { > > if (max_pixclk > 2 * 158400) > > return 316800; > > else if (max_pixclk > 2 * 79200) > > return 158400; > > else > > return 79200; > > } > > > > [1] Geminilake Clocks > > "158.4 MHz CD (cannot be used when audio is enabled and Azalia BCLK is > > 96 MHz) > > 316.8 MHz CD > > 79.2 MHz CD (exclusively for resolutions up to 1080p in low power single > > pipe eDP/MIPI configurations, no audio support)" > > Argh. So it's really about the cdclk freq vs. bclk. Apparently the fact > that the pipe can output two pixels per clock doesn't extend to the HDA > side. OK, then the code looks correct. > > But how do we know the bclk is really 96Mhz? Or are we just making a > worst case estimate here? Base on the hda spec I think bclk should typically > be 24 MHz, but of course the hda spec is so old that it probably has > little to do with today's realities. I guess ideally we'd like the audio > driver to tell us what the frequency is, or we'd dig that up from > somewhere ourselves. > > Hmm. AUD_FREQ_CNTRL seems to have something. 96 vs. 48 MHz. But I'm not sure > we could trust that at boot time. Not sure if the audio driver will make > its own choice if BCLK somewhere. Can any alsa folks help us? Well, I'm not sure which BCLK is referred in this context, but if it's about HD-audio (aka Azalia) BCLK, it's always 24MHz. It's the specification, AFAIK. Takashi
On Thu, Mar 30, 2017 at 02:17:15PM +0200, Takashi Iwai wrote: > On Thu, 30 Mar 2017 13:42:09 +0200, > Ville Syrjälä wrote: > > > > On Wed, Mar 29, 2017 at 09:16:36PM +0000, Pandiyan, Dhinakaran wrote: > > > On Wed, 2017-03-29 at 11:50 +0300, Ville Syrjälä wrote: > > > > On Tue, Mar 07, 2017 at 04:12:52PM -0800, Dhinakaran Pandiyan wrote: > > > > > According to BSpec, "The CD clock frequency must be at least twice the > > > > > frequency of the Azalia BCLK." and BCLK is configured to 96 MHz by > > > > > default. This check is needed because BXT and GLK support cdclk > > > > > frequencies less than 192 MHz. > > > > > > > > > > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > > > > --- > > > > > drivers/gpu/drm/i915/intel_cdclk.c | 12 ++++++++++++ > > > > > 1 file changed, 12 insertions(+) > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c > > > > > index e8c1181..7b1ac1d 100644 > > > > > --- a/drivers/gpu/drm/i915/intel_cdclk.c > > > > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c > > > > > @@ -1458,6 +1458,18 @@ static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state, > > > > > pixel_rate = max(432000, pixel_rate); > > > > > } > > > > > > > > > > + /* According to BSpec, "The CD clock frequency must be at least twice > > > > > + * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default. > > > > > + * The check for GLK has to be adjusted as the platform can output > > > > > + * two pixels per clock. > > > > > + */ > > > > > + if (crtc_state->has_audio) { > > > > > + if (IS_GEMINILAKE(dev_priv)) > > > > > + pixel_rate = max(2 * 2 * 96000, pixel_rate); > > > > > > > > BTW that x2 factor for GLK looks wrong. It should be /2. > > > > > > > > https://bugs.freedesktop.org/show_bug.cgi?id=100439 > > > > > > > > > > BSpec[1] says cdclk needs to be > 2*96 MHz (azalia bclk). To set a cdclk > > > > 192 MHz on GLK, we need to pass in max_pixclk = 2*192 MHz. But with a > > > factor of /2, we can end up picking 158.4 MHz or 79.2 MHz for cdclk, > > > which are lower than 192 MHz. > > > > > > > > > static int glk_calc_cdclk(int max_pixclk) > > > { > > > if (max_pixclk > 2 * 158400) > > > return 316800; > > > else if (max_pixclk > 2 * 79200) > > > return 158400; > > > else > > > return 79200; > > > } > > > > > > [1] Geminilake Clocks > > > "158.4 MHz CD (cannot be used when audio is enabled and Azalia BCLK is > > > 96 MHz) > > > 316.8 MHz CD > > > 79.2 MHz CD (exclusively for resolutions up to 1080p in low power single > > > pipe eDP/MIPI configurations, no audio support)" > > > > Argh. So it's really about the cdclk freq vs. bclk. Apparently the fact > > that the pipe can output two pixels per clock doesn't extend to the HDA > > side. OK, then the code looks correct. > > > > But how do we know the bclk is really 96Mhz? Or are we just making a > > worst case estimate here? Base on the hda spec I think bclk should typically > > be 24 MHz, but of course the hda spec is so old that it probably has > > little to do with today's realities. I guess ideally we'd like the audio > > driver to tell us what the frequency is, or we'd dig that up from > > somewhere ourselves. > > > > Hmm. AUD_FREQ_CNTRL seems to have something. 96 vs. 48 MHz. But I'm not sure > > we could trust that at boot time. Not sure if the audio driver will make > > its own choice if BCLK somewhere. Can any alsa folks help us? > > Well, I'm not sure which BCLK is referred in this context, but if it's > about HD-audio (aka Azalia) BCLK, it's always 24MHz. It's the > specification, AFAIK. That's what I read also. But considering the HDA spec is so dated (doesn't even have the MST stuff in it) I can't be sure it matches any current realities. The spec quote from DK clearly shows that the CDCLK programming section of our spec clearly seems to make provisions for a 96MHz Azalia BCLK. If I look at the AUD_FREQ_CNTRL register I see the following: "Audio BCLK Frequency Control ... [4] 96MHz BCLK Default Value: 1b Indicates that iDISPLAY Audio Link will run at 96MHz. This bit is defaulted to 1. BIOS or System Software must pre-program B96 before the iDISPLAY Audio Link is brought out from reset. [3] 48MHz BCLK Default Value: 0b Indicates that iDISPLAY Audio Link will run at 48MHz. This bit is defaulted to 0. BIOS or System Software must pre-program B96 before the iDISPLAY Audio Link is brought out from reset." Whether this iDISPLAY BCLK has anything to do with the Azalia BCLK I don't know. Maybe they changed it from the standard 24 MHz since it's all internal now and thus no need to interface with external parts?
On Thu, 2017-03-30 at 15:44 +0300, Ville Syrjälä wrote: > On Thu, Mar 30, 2017 at 02:17:15PM +0200, Takashi Iwai wrote: > > On Thu, 30 Mar 2017 13:42:09 +0200, > > Ville Syrjälä wrote: > > > > > > On Wed, Mar 29, 2017 at 09:16:36PM +0000, Pandiyan, Dhinakaran wrote: > > > > On Wed, 2017-03-29 at 11:50 +0300, Ville Syrjälä wrote: > > > > > On Tue, Mar 07, 2017 at 04:12:52PM -0800, Dhinakaran Pandiyan wrote: > > > > > > According to BSpec, "The CD clock frequency must be at least twice the > > > > > > frequency of the Azalia BCLK." and BCLK is configured to 96 MHz by > > > > > > default. This check is needed because BXT and GLK support cdclk > > > > > > frequencies less than 192 MHz. > > > > > > > > > > > > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > > > > > --- > > > > > > drivers/gpu/drm/i915/intel_cdclk.c | 12 ++++++++++++ > > > > > > 1 file changed, 12 insertions(+) > > > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c > > > > > > index e8c1181..7b1ac1d 100644 > > > > > > --- a/drivers/gpu/drm/i915/intel_cdclk.c > > > > > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c > > > > > > @@ -1458,6 +1458,18 @@ static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state, > > > > > > pixel_rate = max(432000, pixel_rate); > > > > > > } > > > > > > > > > > > > + /* According to BSpec, "The CD clock frequency must be at least twice > > > > > > + * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default. > > > > > > + * The check for GLK has to be adjusted as the platform can output > > > > > > + * two pixels per clock. > > > > > > + */ > > > > > > + if (crtc_state->has_audio) { > > > > > > + if (IS_GEMINILAKE(dev_priv)) > > > > > > + pixel_rate = max(2 * 2 * 96000, pixel_rate); > > > > > > > > > > BTW that x2 factor for GLK looks wrong. It should be /2. > > > > > > > > > > https://bugs.freedesktop.org/show_bug.cgi?id=100439 > > > > > > > > > > > > > BSpec[1] says cdclk needs to be > 2*96 MHz (azalia bclk). To set a cdclk > > > > > 192 MHz on GLK, we need to pass in max_pixclk = 2*192 MHz. But with a > > > > factor of /2, we can end up picking 158.4 MHz or 79.2 MHz for cdclk, > > > > which are lower than 192 MHz. > > > > > > > > > > > > static int glk_calc_cdclk(int max_pixclk) > > > > { > > > > if (max_pixclk > 2 * 158400) > > > > return 316800; > > > > else if (max_pixclk > 2 * 79200) > > > > return 158400; > > > > else > > > > return 79200; > > > > } > > > > > > > > [1] Geminilake Clocks > > > > "158.4 MHz CD (cannot be used when audio is enabled and Azalia BCLK is > > > > 96 MHz) > > > > 316.8 MHz CD > > > > 79.2 MHz CD (exclusively for resolutions up to 1080p in low power single > > > > pipe eDP/MIPI configurations, no audio support)" > > > > > > Argh. So it's really about the cdclk freq vs. bclk. Apparently the fact > > > that the pipe can output two pixels per clock doesn't extend to the HDA > > > side. OK, then the code looks correct. > > > > > > But how do we know the bclk is really 96Mhz? Or are we just making a > > > worst case estimate here? Base on the hda spec I think bclk should typically > > > be 24 MHz, but of course the hda spec is so old that it probably has > > > little to do with today's realities. I guess ideally we'd like the audio > > > driver to tell us what the frequency is, or we'd dig that up from > > > somewhere ourselves. > > > > > > Hmm. AUD_FREQ_CNTRL seems to have something. 96 vs. 48 MHz. But I'm not sure > > > we could trust that at boot time. Not sure if the audio driver will make > > > its own choice if BCLK somewhere. Can any alsa folks help us? > > > > Well, I'm not sure which BCLK is referred in this context, but if it's > > about HD-audio (aka Azalia) BCLK, it's always 24MHz. It's the > > specification, AFAIK. > > That's what I read also. But considering the HDA spec is so dated > (doesn't even have the MST stuff in it) I can't be sure it matches > any current realities. > > The spec quote from DK clearly shows that the CDCLK programming section > of our spec clearly seems to make provisions for a 96MHz Azalia BCLK. > > If I look at the AUD_FREQ_CNTRL register I see the following: > "Audio BCLK Frequency Control > ... > [4] 96MHz BCLK > Default Value: 1b > Indicates that iDISPLAY Audio Link will run at 96MHz. This bit is > defaulted to 1. BIOS or System Software must pre-program B96 before the > iDISPLAY Audio Link is brought out from reset. > [3] 48MHz BCLK > Default Value: 0b > Indicates that iDISPLAY Audio Link will run at 48MHz. This bit is > defaulted to 0. BIOS or System Software must pre-program B96 before the > iDISPLAY Audio Link is brought out from reset." > > Whether this iDISPLAY BCLK has anything to do with the Azalia BCLK > I don't know. Maybe they changed it from the standard 24 MHz since it's > all internal now and thus no need to interface with external parts? > Libin was working on a patch that was reading the bclk frequency, looks like he has submitted this https://patchwork.kernel.org/patch/9608123/ We could add a new acomp->audio_ops function to get the exact bclk frequency from the audio driver. -DK
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c index e8c1181..7b1ac1d 100644 --- a/drivers/gpu/drm/i915/intel_cdclk.c +++ b/drivers/gpu/drm/i915/intel_cdclk.c @@ -1458,6 +1458,18 @@ static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state, pixel_rate = max(432000, pixel_rate); } + /* According to BSpec, "The CD clock frequency must be at least twice + * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default. + * The check for GLK has to be adjusted as the platform can output + * two pixels per clock. + */ + if (crtc_state->has_audio) { + if (IS_GEMINILAKE(dev_priv)) + pixel_rate = max(2 * 2 * 96000, pixel_rate); + if (IS_BROXTON(dev_priv)) + pixel_rate = max(2 * 96000, pixel_rate); + } + return pixel_rate; }
According to BSpec, "The CD clock frequency must be at least twice the frequency of the Azalia BCLK." and BCLK is configured to 96 MHz by default. This check is needed because BXT and GLK support cdclk frequencies less than 192 MHz. Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> --- drivers/gpu/drm/i915/intel_cdclk.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)