| Message ID | 20170310022238.3191-1-zhenyuw@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Mar 10, 2017 at 10:22:38AM +0800, Zhenyu Wang wrote: > From commit a6508ded2a66 ("drm/i915: Use page coloring to provide the guard > page at the end of the GTT"), we no longer explicitly subtract guard page > at end for GGTT address space init, so shouldn't subtract that for vGPU > balloon too, as that will leave that end page to be available for > vGPU. Change balloon to cover full range too. > > This fixes to use recent drm-intel tip kernel for guest OS. Found by GVT-g > cmd parser that guest kernel uses end page as scratch then try to run > MI_STORE_REG_MEM onto it. > > v2: remove old comments > > Cc: Terrence Xu <terrence.xu@intel.com> > Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> -Chris
On 2017.03.13 13:39:18 +0000, Chris Wilson wrote: > On Fri, Mar 10, 2017 at 10:22:38AM +0800, Zhenyu Wang wrote: > > From commit a6508ded2a66 ("drm/i915: Use page coloring to provide the guard > > page at the end of the GTT"), we no longer explicitly subtract guard page > > at end for GGTT address space init, so shouldn't subtract that for vGPU > > balloon too, as that will leave that end page to be available for > > vGPU. Change balloon to cover full range too. > > > > This fixes to use recent drm-intel tip kernel for guest OS. Found by GVT-g > > cmd parser that guest kernel uses end page as scratch then try to run > > MI_STORE_REG_MEM onto it. > > > > v2: remove old comments > > > > Cc: Terrence Xu <terrence.xu@intel.com> > > Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> > Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> ping for commit to dinq, as required to run lastest drm-intel in guest.
On Fri, Mar 17, 2017 at 05:25:35PM +0800, Zhenyu Wang wrote: > On 2017.03.13 13:39:18 +0000, Chris Wilson wrote: > > On Fri, Mar 10, 2017 at 10:22:38AM +0800, Zhenyu Wang wrote: > > > From commit a6508ded2a66 ("drm/i915: Use page coloring to provide the guard > > > page at the end of the GTT"), we no longer explicitly subtract guard page > > > at end for GGTT address space init, so shouldn't subtract that for vGPU > > > balloon too, as that will leave that end page to be available for > > > vGPU. Change balloon to cover full range too. > > > > > > This fixes to use recent drm-intel tip kernel for guest OS. Found by GVT-g > > > cmd parser that guest kernel uses end page as scratch then try to run > > > MI_STORE_REG_MEM onto it. > > > > > > v2: remove old comments > > > > > > Cc: Terrence Xu <terrence.xu@intel.com> > > > Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> > > Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> > > ping for commit to dinq, as required to run lastest drm-intel in guest. Applied, I had assumed you would pick up the gvt tree. -Chris
On 2017.03.17 09:42:37 +0000, Chris Wilson wrote: > On Fri, Mar 17, 2017 at 05:25:35PM +0800, Zhenyu Wang wrote: > > On 2017.03.13 13:39:18 +0000, Chris Wilson wrote: > > > On Fri, Mar 10, 2017 at 10:22:38AM +0800, Zhenyu Wang wrote: > > > > From commit a6508ded2a66 ("drm/i915: Use page coloring to provide the guard > > > > page at the end of the GTT"), we no longer explicitly subtract guard page > > > > at end for GGTT address space init, so shouldn't subtract that for vGPU > > > > balloon too, as that will leave that end page to be available for > > > > vGPU. Change balloon to cover full range too. > > > > > > > > This fixes to use recent drm-intel tip kernel for guest OS. Found by GVT-g > > > > cmd parser that guest kernel uses end page as scratch then try to run > > > > MI_STORE_REG_MEM onto it. > > > > > > > > v2: remove old comments > > > > > > > > Cc: Terrence Xu <terrence.xu@intel.com> > > > > Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> > > > Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> > > > > ping for commit to dinq, as required to run lastest drm-intel in guest. > > Applied, I had assumed you would pick up the gvt tree. oh, no, this depends on i915 change, so should align there.
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c index 14014068dfcf..4ab8a973b61f 100644 --- a/drivers/gpu/drm/i915/i915_vgpu.c +++ b/drivers/gpu/drm/i915/i915_vgpu.c @@ -218,13 +218,9 @@ int intel_vgt_balloon(struct drm_i915_private *dev_priv) goto err; } - /* - * No need to partition out the last physical page, - * because it is reserved to the guard page. - */ - if (unmappable_end < ggtt_end - PAGE_SIZE) { + if (unmappable_end < ggtt_end) { ret = vgt_balloon_space(ggtt, &bl_info.space[3], - unmappable_end, ggtt_end - PAGE_SIZE); + unmappable_end, ggtt_end); if (ret) goto err; }
From commit a6508ded2a66 ("drm/i915: Use page coloring to provide the guard page at the end of the GTT"), we no longer explicitly subtract guard page at end for GGTT address space init, so shouldn't subtract that for vGPU balloon too, as that will leave that end page to be available for vGPU. Change balloon to cover full range too. This fixes to use recent drm-intel tip kernel for guest OS. Found by GVT-g cmd parser that guest kernel uses end page as scratch then try to run MI_STORE_REG_MEM onto it. v2: remove old comments Cc: Terrence Xu <terrence.xu@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> --- drivers/gpu/drm/i915/i915_vgpu.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-)