| Message ID | 1308732405-16664-5-git-send-email-kgene.kim@samsung.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, Jun 22, 2011 at 05:46:42PM +0900, Kukjin Kim wrote: > diff --git a/arch/arm/mach-exynos4/sleep.S b/arch/arm/mach-exynos4/sleep.S > index 6b62425..d55d38c 100644 > --- a/arch/arm/mach-exynos4/sleep.S > +++ b/arch/arm/mach-exynos4/sleep.S > @@ -45,11 +45,20 @@ ENTRY(s3c_cpu_save) > ldr r3, =resume_with_mmu > bl cpu_suspend > > - ldr r0, =pm_cpu_sleep > - ldr r0, [ r0 ] > - mov pc, r0 > + bl exynos4_cpu_suspend > + > + /* Restore original sp */ > + mov r0, sp > + add r0, r0, #4 > + ldr sp, [r0] > + > + mov r0, #0 > + b early_wakeup > > resume_with_mmu: > + mov r0, #1 > + > +early_wakeup: > ldmfd sp!, { r3 - r12, pc } NAK. If we want to return from cpu_suspend() stuff then we need to solve this properly, as per my patch sent around 13th June to the hibernate thread. Stop bodging stuff (like you have for the SCU stuff.) and start _talking_ to people if the code doesn't do what you need it to do.
Russell King - ARM Linux wrote: > Stop bodging stuff (like you have for the SCU stuff.) and start _talking_ > to people if the code doesn't do what you need it to do. Hi Russell and all, I'd like to share requirement of EXYNOS4210 PM. Now if there is wakeup source which is pending before entering suspend mode, PMU(Power Management Unit) handles WFI instruction as NOP on EXYNOS4210. But it seems that current cpu_suspend() cannot support this. So how can/should we handle this case? And this is another case. For example, assume that ARM is power down mode and outer cache(L2 cache) data is retention state to use L2 cache data after wakeup. In this case, according to wakeup sequence, firstly L1 cache is enabled in cpu_resume() then L2 cache will be enabled which is implemented in Samsung SoC specific code. So how can be handled the coherency problem between L1 cache and L2 cache? Thanks. Best regards, Kgene. -- Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.
On Fri, Jun 24, 2011 at 04:42:26PM +0900, Kukjin Kim wrote: > Russell King - ARM Linux wrote: > > > Stop bodging stuff (like you have for the SCU stuff.) and start _talking_ > > to people if the code doesn't do what you need it to do. > > Hi Russell and all, > > I'd like to share requirement of EXYNOS4210 PM. > > Now if there is wakeup source which is pending before entering suspend mode, > PMU(Power Management Unit) handles WFI instruction as NOP on EXYNOS4210. But > it seems that current cpu_suspend() cannot support this. So how can/should > we handle this case? See patch from June 13th posted to the hibernate thread. This allows the finisher function to return, though it should only return if it is certain that the system will not enter suspend. Is this true of the current exynos4 code? It seems that the current code will panic() if the WFI is executed as a NOP. > And this is another case. For example, assume that ARM is power down mode > and outer cache(L2 cache) data is retention state to use L2 cache data after > wakeup. In this case, according to wakeup sequence, firstly L1 cache is > enabled in cpu_resume() then L2 cache will be enabled which is implemented > in Samsung SoC specific code. So how can be handled the coherency problem > between L1 cache and L2 cache? You could ensure that L2 is ready to be re-enabled before calling cpu_resume. As the C bit in the control register will be cleared, L2 should not be used at that point, until after the MMU is re- initialized.
Russell King - ARM Linux wrote: > > > > Hi Russell and all, > > > > I'd like to share requirement of EXYNOS4210 PM. > > > > Now if there is wakeup source which is pending before entering suspend mode, > > PMU(Power Management Unit) handles WFI instruction as NOP on EXYNOS4210. > But > > it seems that current cpu_suspend() cannot support this. So how can/should > > we handle this case? > > See patch from June 13th posted to the hibernate thread. This allows > the finisher function to return, though it should only return if it is > certain that the system will not enter suspend. > > Is this true of the current exynos4 code? It seems that the current > code will panic() if the WFI is executed as a NOP. > Yes, you're right, current code cannot control it. Supporting this case will be scheduled in next patch. > > And this is another case. For example, assume that ARM is power down mode > > and outer cache(L2 cache) data is retention state to use L2 cache data after > > wakeup. In this case, according to wakeup sequence, firstly L1 cache is > > enabled in cpu_resume() then L2 cache will be enabled which is implemented > > in Samsung SoC specific code. So how can be handled the coherency problem > > between L1 cache and L2 cache? > > You could ensure that L2 is ready to be re-enabled before calling > cpu_resume. As the C bit in the control register will be cleared, > L2 should not be used at that point, until after the MMU is re- > initialized. Russell, thanks for your kindly explanation :) Best regards, Kgene. -- Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.
diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c index bf53588..f4d52b5 100644 --- a/arch/arm/mach-exynos4/pm.c +++ b/arch/arm/mach-exynos4/pm.c @@ -241,7 +241,6 @@ static struct sleep_save exynos4_l2cc_save[] = { void exynos4_cpu_suspend(void) { unsigned long tmp; - unsigned long mask = 0xFFFFFFFF; /* Setting Central Sequence Register for power down mode */ @@ -249,33 +248,10 @@ void exynos4_cpu_suspend(void) tmp &= ~(S5P_CENTRAL_LOWPWR_CFG); __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); - /* Setting Central Sequence option Register */ - - tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION); - tmp &= ~(S5P_USE_MASK); - tmp |= S5P_USE_STANDBY_WFI0; - __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION); - - /* Clear all interrupt pending to avoid early wakeup */ - - __raw_writel(mask, (S5P_VA_GIC_DIST + 0x280)); - __raw_writel(mask, (S5P_VA_GIC_DIST + 0x284)); - __raw_writel(mask, (S5P_VA_GIC_DIST + 0x288)); - - /* Disable all interrupt */ - - __raw_writel(0x0, (S5P_VA_GIC_CPU + 0x000)); - __raw_writel(0x0, (S5P_VA_GIC_DIST + 0x000)); - __raw_writel(mask, (S5P_VA_GIC_DIST + 0x184)); - __raw_writel(mask, (S5P_VA_GIC_DIST + 0x188)); - outer_flush_all(); /* issue the standby signal into the pm unit. */ cpu_do_idle(); - - /* we should never get past here */ - panic("sleep resumed to originator?"); } static void exynos4_pm_prepare(void) @@ -353,6 +329,22 @@ arch_initcall(exynos4_pm_drvinit); static void exynos4_pm_resume(void) { + unsigned long tmp; + + /* + * If PMU failed while entering sleep mode, WFI will be + * ignored by PMU and then exiting cpu_do_idle(). + * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically + * in this situation. + */ + tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); + if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) { + tmp |= S5P_CENTRAL_LOWPWR_CFG; + __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); + /* No need to perform below restore code */ + goto early_wakeup; + } + /* For release retention */ __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION); @@ -373,6 +365,9 @@ static void exynos4_pm_resume(void) /* enable L2X0*/ writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL); #endif + +early_wakeup: + return; } static struct syscore_ops exynos4_pm_syscore_ops = { diff --git a/arch/arm/mach-exynos4/sleep.S b/arch/arm/mach-exynos4/sleep.S index 6b62425..d55d38c 100644 --- a/arch/arm/mach-exynos4/sleep.S +++ b/arch/arm/mach-exynos4/sleep.S @@ -45,11 +45,20 @@ ENTRY(s3c_cpu_save) ldr r3, =resume_with_mmu bl cpu_suspend - ldr r0, =pm_cpu_sleep - ldr r0, [ r0 ] - mov pc, r0 + bl exynos4_cpu_suspend + + /* Restore original sp */ + mov r0, sp + add r0, r0, #4 + ldr sp, [r0] + + mov r0, #0 + b early_wakeup resume_with_mmu: + mov r0, #1 + +early_wakeup: ldmfd sp!, { r3 - r12, pc } .ltorg