| Message ID | 1491054836-30488-19-git-send-email-yi.y.sun@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
>>> On 01.04.17 at 15:53, <yi.y.sun@linux.intel.com> wrote: > @@ -304,10 +305,14 @@ static void cat_init_feature(const struct cpuid_leaf *regs, > switch ( type ) > { > case PSR_SOCKET_L3_CAT: > + case PSR_SOCKET_L2_CAT: > /* cos=0 is reserved as default cbm(all bits within cbm_len are 1). */ > feat->cos_reg_val[0] = cat_default_val(feat->props->cbm_len); > > - feat->props->type[0] = PSR_CBM_TYPE_L3; > + if ( type == PSR_SOCKET_L3_CAT ) > + feat->props->type[0] = PSR_CBM_TYPE_L3; > + else > + feat->props->type[0] = PSR_CBM_TYPE_L2; Can I talk you into preferring conditional expressions in case like this or ... > @@ -315,7 +320,11 @@ static void cat_init_feature(const struct cpuid_leaf *regs, > */ > for ( i = 1; i <= feat->props->cos_max; i++ ) > { > - wrmsrl(MSR_IA32_PSR_L3_MASK(i), feat->cos_reg_val[0]); > + if ( type == PSR_SOCKET_L3_CAT ) > + wrmsrl(MSR_IA32_PSR_L3_MASK(i), feat->cos_reg_val[0]); > + else > + wrmsrl(MSR_IA32_PSR_L2_MASK(i), feat->cos_reg_val[0]); ... this? Jan
On 17-04-12 09:18:51, Jan Beulich wrote: > >>> On 01.04.17 at 15:53, <yi.y.sun@linux.intel.com> wrote: > > @@ -304,10 +305,14 @@ static void cat_init_feature(const struct cpuid_leaf *regs, > > switch ( type ) > > { > > case PSR_SOCKET_L3_CAT: > > + case PSR_SOCKET_L2_CAT: > > /* cos=0 is reserved as default cbm(all bits within cbm_len are 1). */ > > feat->cos_reg_val[0] = cat_default_val(feat->props->cbm_len); > > > > - feat->props->type[0] = PSR_CBM_TYPE_L3; > > + if ( type == PSR_SOCKET_L3_CAT ) > > + feat->props->type[0] = PSR_CBM_TYPE_L3; > > + else > > + feat->props->type[0] = PSR_CBM_TYPE_L2; > > Can I talk you into preferring conditional expressions in case like > this or ... > > > @@ -315,7 +320,11 @@ static void cat_init_feature(const struct cpuid_leaf *regs, > > */ > > for ( i = 1; i <= feat->props->cos_max; i++ ) > > { > > - wrmsrl(MSR_IA32_PSR_L3_MASK(i), feat->cos_reg_val[0]); > > + if ( type == PSR_SOCKET_L3_CAT ) > > + wrmsrl(MSR_IA32_PSR_L3_MASK(i), feat->cos_reg_val[0]); > > + else > > + wrmsrl(MSR_IA32_PSR_L2_MASK(i), feat->cos_reg_val[0]); > > ... this? > I think you mean '?:', right? > Jan
>>> On 13.04.17 at 10:12, <yi.y.sun@linux.intel.com> wrote: > On 17-04-12 09:18:51, Jan Beulich wrote: >> >>> On 01.04.17 at 15:53, <yi.y.sun@linux.intel.com> wrote: >> > @@ -304,10 +305,14 @@ static void cat_init_feature(const struct cpuid_leaf > *regs, >> > switch ( type ) >> > { >> > case PSR_SOCKET_L3_CAT: >> > + case PSR_SOCKET_L2_CAT: >> > /* cos=0 is reserved as default cbm(all bits within cbm_len are > 1). */ >> > feat->cos_reg_val[0] = cat_default_val(feat->props->cbm_len); >> > >> > - feat->props->type[0] = PSR_CBM_TYPE_L3; >> > + if ( type == PSR_SOCKET_L3_CAT ) >> > + feat->props->type[0] = PSR_CBM_TYPE_L3; >> > + else >> > + feat->props->type[0] = PSR_CBM_TYPE_L2; >> >> Can I talk you into preferring conditional expressions in case like >> this or ... >> >> > @@ -315,7 +320,11 @@ static void cat_init_feature(const struct cpuid_leaf *regs, >> > */ >> > for ( i = 1; i <= feat->props->cos_max; i++ ) >> > { >> > - wrmsrl(MSR_IA32_PSR_L3_MASK(i), feat->cos_reg_val[0]); >> > + if ( type == PSR_SOCKET_L3_CAT ) >> > + wrmsrl(MSR_IA32_PSR_L3_MASK(i), feat->cos_reg_val[0]); >> > + else >> > + wrmsrl(MSR_IA32_PSR_L2_MASK(i), feat->cos_reg_val[0]); >> >> ... this? >> > I think you mean '?:', right? Yes, that's what "conditional expression" is according to the C standard. Jan
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c index bfa1777..6a9cd88 100644 --- a/xen/arch/x86/psr.c +++ b/xen/arch/x86/psr.c @@ -160,6 +160,7 @@ static DEFINE_PER_CPU(struct psr_assoc, psr_assoc); */ static struct feat_node *feat_l3_cat; static struct feat_node *feat_l3_cdp; +static struct feat_node *feat_l2_cat; /* Common functions */ #define cat_default_val(len) (0xffffffff >> (32 - (len))) @@ -304,10 +305,14 @@ static void cat_init_feature(const struct cpuid_leaf *regs, switch ( type ) { case PSR_SOCKET_L3_CAT: + case PSR_SOCKET_L2_CAT: /* cos=0 is reserved as default cbm(all bits within cbm_len are 1). */ feat->cos_reg_val[0] = cat_default_val(feat->props->cbm_len); - feat->props->type[0] = PSR_CBM_TYPE_L3; + if ( type == PSR_SOCKET_L3_CAT ) + feat->props->type[0] = PSR_CBM_TYPE_L3; + else + feat->props->type[0] = PSR_CBM_TYPE_L2; /* * To handle cpu offline and then online case, we need restore MSRs to @@ -315,7 +320,11 @@ static void cat_init_feature(const struct cpuid_leaf *regs, */ for ( i = 1; i <= feat->props->cos_max; i++ ) { - wrmsrl(MSR_IA32_PSR_L3_MASK(i), feat->cos_reg_val[0]); + if ( type == PSR_SOCKET_L3_CAT ) + wrmsrl(MSR_IA32_PSR_L3_MASK(i), feat->cos_reg_val[0]); + else + wrmsrl(MSR_IA32_PSR_L2_MASK(i), feat->cos_reg_val[0]); + feat->cos_reg_val[i] = feat->cos_reg_val[0]; } @@ -454,6 +463,11 @@ static struct feat_props l3_cdp_props = { .write_msr = l3_cdp_write_msr, }; +/* L2 CAT ops */ +static struct feat_props l2_cat_props = { + .cos_num = 1, +}; + static void __init parse_psr_bool(char *s, char *value, char *feature, unsigned int mask) { @@ -1393,6 +1407,10 @@ static int psr_cpu_prepare(void) (feat_l3_cdp = xzalloc(struct feat_node)) == NULL ) return -ENOMEM; + if ( feat_l2_cat == NULL && + (feat_l2_cat = xzalloc(struct feat_node)) == NULL ) + return -ENOMEM; + return 0; } @@ -1442,6 +1460,17 @@ static void psr_cpu_init(void) } } + cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 0, ®s); + if ( regs.b & PSR_RESOURCE_TYPE_L2 ) + { + cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 2, ®s); + + feat = feat_l2_cat; + feat_l2_cat = NULL; + feat->props = &l2_cat_props; + cat_init_feature(®s, feat, info, PSR_SOCKET_L2_CAT); + } + assoc_init: psr_assoc_init(); } diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h index 771e750..6c49c6d 100644 --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -345,6 +345,7 @@ #define MSR_IA32_PSR_L3_MASK(n) (0x00000c90 + (n)) #define MSR_IA32_PSR_L3_MASK_CODE(n) (0x00000c90 + (n) * 2 + 1) #define MSR_IA32_PSR_L3_MASK_DATA(n) (0x00000c90 + (n) * 2) +#define MSR_IA32_PSR_L2_MASK(n) (0x00000d10 + (n)) /* Intel Model 6 */ #define MSR_P6_PERFCTR(n) (0x000000c1 + (n)) diff --git a/xen/include/asm-x86/psr.h b/xen/include/asm-x86/psr.h index 66d5218..e576f27 100644 --- a/xen/include/asm-x86/psr.h +++ b/xen/include/asm-x86/psr.h @@ -23,6 +23,7 @@ /* Resource Type Enumeration */ #define PSR_RESOURCE_TYPE_L3 0x2 +#define PSR_RESOURCE_TYPE_L2 0x4 /* L3 Monitoring Features */ #define PSR_CMT_L3_OCCUPANCY 0x1 @@ -56,6 +57,7 @@ enum cbm_type { PSR_CBM_TYPE_L3, PSR_CBM_TYPE_L3_CODE, PSR_CBM_TYPE_L3_DATA, + PSR_CBM_TYPE_L2, }; extern struct psr_cmt *psr_cmt;
This patch implements the CPU init and free flow for L2 CAT. Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com> --- v10: - implement L2 CAT case in 'cat_init_feature'. (suggested by Jan Beulich) - changes about 'props'. (suggested by Jan Beulich) - introduce 'PSR_CBM_TYPE_L2'. v9: - modify error handling process in 'psr_cpu_prepare' to reduce redundant codes. - reuse 'cat_init_feature' and 'cat_get_cos_max' for L2 CAT to reduce redundant codes. (suggested by Roger Pau) - remove unnecessary comment. (suggested by Jan Beulich) - move L2 CAT related codes from 'cpu_init_work' into 'psr_cpu_init'. (suggested by Jan Beulich) - do not free resource when allocation fails in 'psr_cpu_prepare'. (suggested by Jan Beulich) v7: - initialize 'l2_cat'. (suggested by Konrad Rzeszutek Wilk) v6: - use 'struct cpuid_leaf'. (suggested by Konrad Rzeszutek Wilk and Jan Beulich) v5: - remove 'feat_l2_cat' free in 'free_feature'. (suggested by Jan Beulich) - encapsulate cpuid registers into 'struct cpuid_leaf_regs'. (suggested by Jan Beulich) - print socket info when 'opt_cpu_info' is true. (suggested by Jan Beulich) - rename 'l2_cat_get_max_cos_max' to 'l2_cat_get_cos_max'. (suggested by Jan Beulich) - rename 'dat[]' to 'data[]' (suggested by Jan Beulich) - move 'cpu_prepare_work' contents into 'psr_cpu_prepare'. (suggested by Jan Beulich) v4: - create this patch because of codes architecture change. (suggested by Jan Beulich) --- xen/arch/x86/psr.c | 33 +++++++++++++++++++++++++++++++-- xen/include/asm-x86/msr-index.h | 1 + xen/include/asm-x86/psr.h | 2 ++ 3 files changed, 34 insertions(+), 2 deletions(-)