| Message ID | 1479710246-26676-8-git-send-email-riteshh@codeaurora.org (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
On Mon, Nov 21, 2016 at 12:07:17PM +0530, Ritesh Harjani wrote: > This add get_min_clock() and get_max_clock() callback > for sdhci-msm. sdhci-msm min/max clocks may be different > hence implement these callbacks. > > Signed-off-by: Sahitya Tummala <stummala@codeaurora.org> > Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> > Acked-by: Adrian Hunter <adrian.hunter@intel.com> This patch needs to be picked up for stable as 4.9 is currently broken w.r.t. MMC on Qualcomm platforms. Fixes: d84be51d1c1d ("mmc: sdhci-msm: Enable few quirks") Regards, Andy Gross -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 04/27/2017 12:44 AM, Andy Gross wrote: > On Mon, Nov 21, 2016 at 12:07:17PM +0530, Ritesh Harjani wrote: >> This add get_min_clock() and get_max_clock() callback >> for sdhci-msm. sdhci-msm min/max clocks may be different >> hence implement these callbacks. >> >> Signed-off-by: Sahitya Tummala <stummala@codeaurora.org> >> Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> >> Acked-by: Adrian Hunter <adrian.hunter@intel.com> > > This patch needs to be picked up for stable as 4.9 is currently broken w.r.t. > MMC on Qualcomm platforms. > > Fixes: d84be51d1c1d ("mmc: sdhci-msm: Enable few quirks") Agree! Applying this patch (80031bdeb764) in stable fixes the broken mmc. Otherwise the following error is seen since v4.9.22: mmc0: Hardware doesn't specify base clock frequency. Thanks, Georgi -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index fc093b8..aaeaf47 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -68,6 +68,8 @@ #define CORE_VENDOR_SPEC_CAPABILITIES0 0x11c +#define SDHCI_MSM_MIN_CLOCK 400000 + #define CDR_SELEXT_SHIFT 20 #define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT) #define CMUX_SHIFT_PHASE_SHIFT 24 @@ -556,6 +558,19 @@ static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data) return IRQ_HANDLED; } +static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); + + return clk_round_rate(msm_host->clk, ULONG_MAX); +} + +static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host) +{ + return SDHCI_MSM_MIN_CLOCK; +} + static const struct of_device_id sdhci_msm_dt_match[] = { { .compatible = "qcom,sdhci-msm-v4" }, {}, @@ -567,6 +582,8 @@ static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data) .platform_execute_tuning = sdhci_msm_execute_tuning, .reset = sdhci_reset, .set_clock = sdhci_set_clock, + .get_min_clock = sdhci_msm_get_min_clock, + .get_max_clock = sdhci_msm_get_max_clock, .set_bus_width = sdhci_set_bus_width, .set_uhs_signaling = sdhci_msm_set_uhs_signaling, .voltage_switch = sdhci_msm_voltage_switch,