| Message ID | 20170508114902.18965-9-mahesh1.kumar@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, May 08, 2017 at 05:18:59PM +0530, Mahesh Kumar wrote: > This patch cleanup/reorganises the watermark calculation functions. > This patch also make use of already available macro > "drm_atomic_crtc_state_for_each_plane_state" to walk through > plane_state list instead of calculating plane_state in function itself. > Now we iterate over WM levels in skl_compute_wm_level function instead > of "skl_build_pipe_wm" function. I'd split the minor cleanup (const-ifying, drm_atomic_crtc_state_for_each_plane_state usage, etc.) into a separate patch from the code flow change (looping over levels in skl_compute_wm_level instead of skl_build_pipe_wm). You'll probably also want to rename the function to skl_compute_wm_level*s* (plural) if its going to calculate all levels now instead of just one. Matt > > This restructuring will help later patch for new DDB allocation > algorithm to do only algo related changes. > > Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 89 +++++++++++++++++------------------------ > 1 file changed, 37 insertions(+), 52 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 0ace94d67432..9d0225862a7e 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3732,7 +3732,7 @@ static uint_fixed_16_16_t skl_wm_method2(uint32_t pixel_rate, > } > > static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate, > - struct intel_plane_state *pstate) > + const struct intel_plane_state *pstate) > { > uint64_t adjusted_pixel_rate; > uint_fixed_16_16_t downscale_amount; > @@ -3754,7 +3754,7 @@ static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cst > > static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, > struct intel_crtc_state *cstate, > - struct intel_plane_state *intel_pstate, > + const struct intel_plane_state *intel_pstate, > uint16_t ddb_allocation, > int level, > uint16_t *out_blocks, /* out */ > @@ -3762,8 +3762,8 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, > bool *enabled /* out */) > { > struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane); > - struct drm_plane_state *pstate = &intel_pstate->base; > - struct drm_framebuffer *fb = pstate->fb; > + const struct drm_plane_state *pstate = &intel_pstate->base; > + const struct drm_framebuffer *fb = pstate->fb; > uint32_t latency = dev_priv->wm.skl_latency[level]; > uint_fixed_16_16_t method1, method2; > uint_fixed_16_16_t plane_blocks_per_line; > @@ -3918,52 +3918,36 @@ static int > skl_compute_wm_level(const struct drm_i915_private *dev_priv, > struct skl_ddb_allocation *ddb, > struct intel_crtc_state *cstate, > - struct intel_plane *intel_plane, > - int level, > - struct skl_wm_level *result) > + const struct intel_plane_state *intel_pstate, > + struct skl_plane_wm *wm) > { > - struct drm_atomic_state *state = cstate->base.state; > struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); > - struct drm_plane *plane = &intel_plane->base; > - struct intel_plane_state *intel_pstate = NULL; > + struct drm_plane *plane = intel_pstate->base.plane; > + struct intel_plane *intel_plane = to_intel_plane(plane); > uint16_t ddb_blocks; > enum pipe pipe = intel_crtc->pipe; > + int level, max_level = ilk_wm_max_level(dev_priv); > int ret; > > - if (state) > - intel_pstate = > - intel_atomic_get_existing_plane_state(state, > - intel_plane); > - > - /* > - * Note: If we start supporting multiple pending atomic commits against > - * the same planes/CRTC's in the future, plane->state will no longer be > - * the correct pre-state to use for the calculations here and we'll > - * need to change where we get the 'unchanged' plane data from. > - * > - * For now this is fine because we only allow one queued commit against > - * a CRTC. Even if the plane isn't modified by this transaction and we > - * don't have a plane lock, we still have the CRTC's lock, so we know > - * that no other transactions are racing with us to update it. > - */ > - if (!intel_pstate) > - intel_pstate = to_intel_plane_state(plane->state); > - > if (WARN_ON(!intel_pstate->base.fb)) > return -EINVAL; > > ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][intel_plane->id]); > > - ret = skl_compute_plane_wm(dev_priv, > - cstate, > - intel_pstate, > - ddb_blocks, > - level, > - &result->plane_res_b, > - &result->plane_res_l, > - &result->plane_en); > - if (ret) > - return ret; > + for (level = 0; level <= max_level; level++) { > + struct skl_wm_level *result = &wm->wm[level]; > + > + ret = skl_compute_plane_wm(dev_priv, > + cstate, > + intel_pstate, > + ddb_blocks, > + level, > + &result->plane_res_b, > + &result->plane_res_l, > + &result->plane_en); > + if (ret) > + return ret; > + } > > return 0; > } > @@ -4009,10 +3993,11 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate, > struct skl_pipe_wm *pipe_wm) > { > struct drm_device *dev = cstate->base.crtc->dev; > + struct drm_crtc_state *crtc_state = &cstate->base; > const struct drm_i915_private *dev_priv = to_i915(dev); > - struct intel_plane *intel_plane; > + struct drm_plane *plane; > + const struct drm_plane_state *pstate; > struct skl_plane_wm *wm; > - int level, max_level = ilk_wm_max_level(dev_priv); > int ret; > > /* > @@ -4021,18 +4006,18 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate, > */ > memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes)); > > - for_each_intel_plane_mask(&dev_priv->drm, > - intel_plane, > - cstate->base.plane_mask) { > - wm = &pipe_wm->planes[intel_plane->id]; > + drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) { > + const struct intel_plane_state *intel_pstate = > + to_intel_plane_state(pstate); > + enum plane_id plane_id = to_intel_plane(plane)->id; > + > + wm = &pipe_wm->planes[plane_id]; > + > + ret = skl_compute_wm_level(dev_priv, ddb, cstate, > + intel_pstate, wm); > + if (ret) > + return ret; > > - for (level = 0; level <= max_level; level++) { > - ret = skl_compute_wm_level(dev_priv, ddb, cstate, > - intel_plane, level, > - &wm->wm[level]); > - if (ret) > - return ret; > - } > skl_compute_transition_wm(cstate, &wm->trans_wm); > } > pipe_wm->linetime = skl_compute_linetime_wm(cstate); > -- > 2.11.0 >
Hi, On Friday 12 May 2017 05:53 AM, Matt Roper wrote: > On Mon, May 08, 2017 at 05:18:59PM +0530, Mahesh Kumar wrote: >> This patch cleanup/reorganises the watermark calculation functions. >> This patch also make use of already available macro >> "drm_atomic_crtc_state_for_each_plane_state" to walk through >> plane_state list instead of calculating plane_state in function itself. >> Now we iterate over WM levels in skl_compute_wm_level function instead >> of "skl_build_pipe_wm" function. > I'd split the minor cleanup (const-ifying, > drm_atomic_crtc_state_for_each_plane_state usage, etc.) into a separate > patch from the code flow change (looping over levels in > skl_compute_wm_level instead of skl_build_pipe_wm). You'll probably > also want to rename the function to skl_compute_wm_level*s* (plural) if > its going to calculate all levels now instead of just one. const-ifying is required by drm_atomic_crtc_state_for_each_plane_state Macro, dividing it into 2 patches one to use the the macro & another one to move level iteration in separate skl_compute_wm_level*s *function. -Mahesh > > > Matt > >> This restructuring will help later patch for new DDB allocation >> algorithm to do only algo related changes. >> >> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> >> --- >> drivers/gpu/drm/i915/intel_pm.c | 89 +++++++++++++++++------------------------ >> 1 file changed, 37 insertions(+), 52 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c >> index 0ace94d67432..9d0225862a7e 100644 >> --- a/drivers/gpu/drm/i915/intel_pm.c >> +++ b/drivers/gpu/drm/i915/intel_pm.c >> @@ -3732,7 +3732,7 @@ static uint_fixed_16_16_t skl_wm_method2(uint32_t pixel_rate, >> } >> >> static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate, >> - struct intel_plane_state *pstate) >> + const struct intel_plane_state *pstate) >> { >> uint64_t adjusted_pixel_rate; >> uint_fixed_16_16_t downscale_amount; >> @@ -3754,7 +3754,7 @@ static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cst >> >> static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, >> struct intel_crtc_state *cstate, >> - struct intel_plane_state *intel_pstate, >> + const struct intel_plane_state *intel_pstate, >> uint16_t ddb_allocation, >> int level, >> uint16_t *out_blocks, /* out */ >> @@ -3762,8 +3762,8 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, >> bool *enabled /* out */) >> { >> struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane); >> - struct drm_plane_state *pstate = &intel_pstate->base; >> - struct drm_framebuffer *fb = pstate->fb; >> + const struct drm_plane_state *pstate = &intel_pstate->base; >> + const struct drm_framebuffer *fb = pstate->fb; >> uint32_t latency = dev_priv->wm.skl_latency[level]; >> uint_fixed_16_16_t method1, method2; >> uint_fixed_16_16_t plane_blocks_per_line; >> @@ -3918,52 +3918,36 @@ static int >> skl_compute_wm_level(const struct drm_i915_private *dev_priv, >> struct skl_ddb_allocation *ddb, >> struct intel_crtc_state *cstate, >> - struct intel_plane *intel_plane, >> - int level, >> - struct skl_wm_level *result) >> + const struct intel_plane_state *intel_pstate, >> + struct skl_plane_wm *wm) >> { >> - struct drm_atomic_state *state = cstate->base.state; >> struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); >> - struct drm_plane *plane = &intel_plane->base; >> - struct intel_plane_state *intel_pstate = NULL; >> + struct drm_plane *plane = intel_pstate->base.plane; >> + struct intel_plane *intel_plane = to_intel_plane(plane); >> uint16_t ddb_blocks; >> enum pipe pipe = intel_crtc->pipe; >> + int level, max_level = ilk_wm_max_level(dev_priv); >> int ret; >> >> - if (state) >> - intel_pstate = >> - intel_atomic_get_existing_plane_state(state, >> - intel_plane); >> - >> - /* >> - * Note: If we start supporting multiple pending atomic commits against >> - * the same planes/CRTC's in the future, plane->state will no longer be >> - * the correct pre-state to use for the calculations here and we'll >> - * need to change where we get the 'unchanged' plane data from. >> - * >> - * For now this is fine because we only allow one queued commit against >> - * a CRTC. Even if the plane isn't modified by this transaction and we >> - * don't have a plane lock, we still have the CRTC's lock, so we know >> - * that no other transactions are racing with us to update it. >> - */ >> - if (!intel_pstate) >> - intel_pstate = to_intel_plane_state(plane->state); >> - >> if (WARN_ON(!intel_pstate->base.fb)) >> return -EINVAL; >> >> ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][intel_plane->id]); >> >> - ret = skl_compute_plane_wm(dev_priv, >> - cstate, >> - intel_pstate, >> - ddb_blocks, >> - level, >> - &result->plane_res_b, >> - &result->plane_res_l, >> - &result->plane_en); >> - if (ret) >> - return ret; >> + for (level = 0; level <= max_level; level++) { >> + struct skl_wm_level *result = &wm->wm[level]; >> + >> + ret = skl_compute_plane_wm(dev_priv, >> + cstate, >> + intel_pstate, >> + ddb_blocks, >> + level, >> + &result->plane_res_b, >> + &result->plane_res_l, >> + &result->plane_en); >> + if (ret) >> + return ret; >> + } >> >> return 0; >> } >> @@ -4009,10 +3993,11 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate, >> struct skl_pipe_wm *pipe_wm) >> { >> struct drm_device *dev = cstate->base.crtc->dev; >> + struct drm_crtc_state *crtc_state = &cstate->base; >> const struct drm_i915_private *dev_priv = to_i915(dev); >> - struct intel_plane *intel_plane; >> + struct drm_plane *plane; >> + const struct drm_plane_state *pstate; >> struct skl_plane_wm *wm; >> - int level, max_level = ilk_wm_max_level(dev_priv); >> int ret; >> >> /* >> @@ -4021,18 +4006,18 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate, >> */ >> memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes)); >> >> - for_each_intel_plane_mask(&dev_priv->drm, >> - intel_plane, >> - cstate->base.plane_mask) { >> - wm = &pipe_wm->planes[intel_plane->id]; >> + drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) { >> + const struct intel_plane_state *intel_pstate = >> + to_intel_plane_state(pstate); >> + enum plane_id plane_id = to_intel_plane(plane)->id; >> + >> + wm = &pipe_wm->planes[plane_id]; >> + >> + ret = skl_compute_wm_level(dev_priv, ddb, cstate, >> + intel_pstate, wm); >> + if (ret) >> + return ret; >> >> - for (level = 0; level <= max_level; level++) { >> - ret = skl_compute_wm_level(dev_priv, ddb, cstate, >> - intel_plane, level, >> - &wm->wm[level]); >> - if (ret) >> - return ret; >> - } >> skl_compute_transition_wm(cstate, &wm->trans_wm); >> } >> pipe_wm->linetime = skl_compute_linetime_wm(cstate); >> -- >> 2.11.0 >>
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 0ace94d67432..9d0225862a7e 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3732,7 +3732,7 @@ static uint_fixed_16_16_t skl_wm_method2(uint32_t pixel_rate, } static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate, - struct intel_plane_state *pstate) + const struct intel_plane_state *pstate) { uint64_t adjusted_pixel_rate; uint_fixed_16_16_t downscale_amount; @@ -3754,7 +3754,7 @@ static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cst static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, struct intel_crtc_state *cstate, - struct intel_plane_state *intel_pstate, + const struct intel_plane_state *intel_pstate, uint16_t ddb_allocation, int level, uint16_t *out_blocks, /* out */ @@ -3762,8 +3762,8 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, bool *enabled /* out */) { struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane); - struct drm_plane_state *pstate = &intel_pstate->base; - struct drm_framebuffer *fb = pstate->fb; + const struct drm_plane_state *pstate = &intel_pstate->base; + const struct drm_framebuffer *fb = pstate->fb; uint32_t latency = dev_priv->wm.skl_latency[level]; uint_fixed_16_16_t method1, method2; uint_fixed_16_16_t plane_blocks_per_line; @@ -3918,52 +3918,36 @@ static int skl_compute_wm_level(const struct drm_i915_private *dev_priv, struct skl_ddb_allocation *ddb, struct intel_crtc_state *cstate, - struct intel_plane *intel_plane, - int level, - struct skl_wm_level *result) + const struct intel_plane_state *intel_pstate, + struct skl_plane_wm *wm) { - struct drm_atomic_state *state = cstate->base.state; struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); - struct drm_plane *plane = &intel_plane->base; - struct intel_plane_state *intel_pstate = NULL; + struct drm_plane *plane = intel_pstate->base.plane; + struct intel_plane *intel_plane = to_intel_plane(plane); uint16_t ddb_blocks; enum pipe pipe = intel_crtc->pipe; + int level, max_level = ilk_wm_max_level(dev_priv); int ret; - if (state) - intel_pstate = - intel_atomic_get_existing_plane_state(state, - intel_plane); - - /* - * Note: If we start supporting multiple pending atomic commits against - * the same planes/CRTC's in the future, plane->state will no longer be - * the correct pre-state to use for the calculations here and we'll - * need to change where we get the 'unchanged' plane data from. - * - * For now this is fine because we only allow one queued commit against - * a CRTC. Even if the plane isn't modified by this transaction and we - * don't have a plane lock, we still have the CRTC's lock, so we know - * that no other transactions are racing with us to update it. - */ - if (!intel_pstate) - intel_pstate = to_intel_plane_state(plane->state); - if (WARN_ON(!intel_pstate->base.fb)) return -EINVAL; ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][intel_plane->id]); - ret = skl_compute_plane_wm(dev_priv, - cstate, - intel_pstate, - ddb_blocks, - level, - &result->plane_res_b, - &result->plane_res_l, - &result->plane_en); - if (ret) - return ret; + for (level = 0; level <= max_level; level++) { + struct skl_wm_level *result = &wm->wm[level]; + + ret = skl_compute_plane_wm(dev_priv, + cstate, + intel_pstate, + ddb_blocks, + level, + &result->plane_res_b, + &result->plane_res_l, + &result->plane_en); + if (ret) + return ret; + } return 0; } @@ -4009,10 +3993,11 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate, struct skl_pipe_wm *pipe_wm) { struct drm_device *dev = cstate->base.crtc->dev; + struct drm_crtc_state *crtc_state = &cstate->base; const struct drm_i915_private *dev_priv = to_i915(dev); - struct intel_plane *intel_plane; + struct drm_plane *plane; + const struct drm_plane_state *pstate; struct skl_plane_wm *wm; - int level, max_level = ilk_wm_max_level(dev_priv); int ret; /* @@ -4021,18 +4006,18 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate, */ memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes)); - for_each_intel_plane_mask(&dev_priv->drm, - intel_plane, - cstate->base.plane_mask) { - wm = &pipe_wm->planes[intel_plane->id]; + drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) { + const struct intel_plane_state *intel_pstate = + to_intel_plane_state(pstate); + enum plane_id plane_id = to_intel_plane(plane)->id; + + wm = &pipe_wm->planes[plane_id]; + + ret = skl_compute_wm_level(dev_priv, ddb, cstate, + intel_pstate, wm); + if (ret) + return ret; - for (level = 0; level <= max_level; level++) { - ret = skl_compute_wm_level(dev_priv, ddb, cstate, - intel_plane, level, - &wm->wm[level]); - if (ret) - return ret; - } skl_compute_transition_wm(cstate, &wm->trans_wm); } pipe_wm->linetime = skl_compute_linetime_wm(cstate);
This patch cleanup/reorganises the watermark calculation functions. This patch also make use of already available macro "drm_atomic_crtc_state_for_each_plane_state" to walk through plane_state list instead of calculating plane_state in function itself. Now we iterate over WM levels in skl_compute_wm_level function instead of "skl_build_pipe_wm" function. This restructuring will help later patch for new DDB allocation algorithm to do only algo related changes. Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 89 +++++++++++++++++------------------------ 1 file changed, 37 insertions(+), 52 deletions(-)