| Message ID | 20170524141035.21031-3-antoine.tenart@free-electrons.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi Antoine, On mer., mai 24 2017, Antoine Tenart <antoine.tenart@free-electrons.com> wrote: > The cryptographic engine nodes have an interrupt which is configured as > both edge and level, which makes no sense at all. Fix this by > configuring it the right way (level). > > Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Applied on mvebu/fixes Thanks, Gregory > --- > arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 3 +-- > arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 3 +-- > 2 files changed, 2 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi > index ac8df5201cd6..b4bc42ece754 100644 > --- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi > +++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi > @@ -231,8 +231,7 @@ > cpm_crypto: crypto@800000 { > compatible = "inside-secure,safexcel-eip197"; > reg = <0x800000 0x200000>; > - interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING > - | IRQ_TYPE_LEVEL_HIGH)>, > + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, > diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi > index 7740a75a8230..6e2058847ddc 100644 > --- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi > +++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi > @@ -221,8 +221,7 @@ > cps_crypto: crypto@800000 { > compatible = "inside-secure,safexcel-eip197"; > reg = <0x800000 0x200000>; > - interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING > - | IRQ_TYPE_LEVEL_HIGH)>, > + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, > -- > 2.9.4 >
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi index ac8df5201cd6..b4bc42ece754 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi @@ -231,8 +231,7 @@ cpm_crypto: crypto@800000 { compatible = "inside-secure,safexcel-eip197"; reg = <0x800000 0x200000>; - interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING - | IRQ_TYPE_LEVEL_HIGH)>, + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi index 7740a75a8230..6e2058847ddc 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi @@ -221,8 +221,7 @@ cps_crypto: crypto@800000 { compatible = "inside-secure,safexcel-eip197"; reg = <0x800000 0x200000>; - interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING - | IRQ_TYPE_LEVEL_HIGH)>, + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
The cryptographic engine nodes have an interrupt which is configured as both edge and level, which makes no sense at all. Fix this by configuring it the right way (level). Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> --- arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 3 +-- arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-)