| Message ID | 20170515075012.3696-1-linus.walleij@linaro.org (mailing list archive) |
|---|---|
| State | Accepted, archived |
| Delegated to: | Andy Gross |
| Headers | show |
On Mon 15 May 00:50 PDT 2017, Linus Walleij wrote: > This defines the memory location and interrupt used by the GSBI8 > I2C adapter on the MSM8660 SoCs. We add it as "disabled" by > default so that boards using this I2C can enable it. > Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Regards, Bjorn -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 05/15, Linus Walleij wrote: > diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi > index 747669a62aa8..a53c0f9970bd 100644 > --- a/arch/arm/boot/dts/qcom-msm8660.dtsi > +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi > @@ -107,6 +107,31 @@ > reg = <0x900000 0x4000>; > }; > > + > + gsbi8: gsbi@19800000 { > + compatible = "qcom,gsbi-v1.0.0"; > + cell-index = <12>; > + reg = <0x19800000 0x100>; > + clocks = <&gcc GSBI8_H_CLK>; > + clock-names = "iface"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + syscon-tcsr = <&tcsr>; > + > + gsbi8_i2c: i2c@19880000 { > + compatible = "qcom,i2c-qup-v1.1.1"; > + reg = <0x19880000 0x1000>; > + interrupts = <0 161 IRQ_TYPE_NONE>; interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>? > + clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>;
On Fri, Jun 02, 2017 at 03:02:23PM -0700, Stephen Boyd wrote: > On 05/15, Linus Walleij wrote: > > diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi > > index 747669a62aa8..a53c0f9970bd 100644 > > --- a/arch/arm/boot/dts/qcom-msm8660.dtsi > > +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi > > @@ -107,6 +107,31 @@ > > reg = <0x900000 0x4000>; > > }; > > > > + > > + gsbi8: gsbi@19800000 { > > + compatible = "qcom,gsbi-v1.0.0"; > > + cell-index = <12>; > > + reg = <0x19800000 0x100>; > > + clocks = <&gcc GSBI8_H_CLK>; > > + clock-names = "iface"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges; > > + > > + syscon-tcsr = <&tcsr>; > > + > > + gsbi8_i2c: i2c@19880000 { > > + compatible = "qcom,i2c-qup-v1.1.1"; > > + reg = <0x19880000 0x1000>; > > + interrupts = <0 161 IRQ_TYPE_NONE>; > > interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>? I'll fix this up. No need for resend -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index 747669a62aa8..a53c0f9970bd 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -107,6 +107,31 @@ reg = <0x900000 0x4000>; }; + + gsbi8: gsbi@19800000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <12>; + reg = <0x19800000 0x100>; + clocks = <&gcc GSBI8_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + + gsbi8_i2c: i2c@19880000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x19880000 0x1000>; + interrupts = <0 161 IRQ_TYPE_NONE>; + clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + gsbi12: gsbi@19c00000 { compatible = "qcom,gsbi-v1.0.0"; cell-index = <12>;
This defines the memory location and interrupt used by the GSBI8 I2C adapter on the MSM8660 SoCs. We add it as "disabled" by default so that boards using this I2C can enable it. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> --- arch/arm/boot/dts/qcom-msm8660.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+)