| Message ID | 20170525030204.126233-2-songxiaowei@hisilicon.com (mailing list archive) |
|---|---|
| State | New, archived |
| Delegated to: | Bjorn Helgaas |
| Headers | show |
On Thu, May 25, 2017 at 11:02:01AM +0800, Xiaowei Song wrote: > Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com> > --- > .../devicetree/bindings/pci/kirin-pcie.txt | 49 ++++++++++++++++++++++ > 1 file changed, 49 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt Looking for an ack from Rob. > diff --git a/Documentation/devicetree/bindings/pci/kirin-pcie.txt b/Documentation/devicetree/bindings/pci/kirin-pcie.txt > new file mode 100644 > index 000000000000..ba6f1bd191f5 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/kirin-pcie.txt > @@ -0,0 +1,49 @@ > +HiSilicon Kirin SoCs PCIe host DT description > + > +Kirin PCIe host controller is based on Designware PCI core. > +It shares common functions with PCIe Designware core driver > +and inherits common properties defined in > +Documentation/devicetree/bindings/pci/designware-pci.txt. > + > +Additional properties are described here: > + > +Required properties > +- compatible: > + "hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC > +- reg: Should contain rc_dbi, apb, phy, config registers location and length. > +- reg-names: Must include the following entries: > + "dbi": controller configuration registers; > + "apb": apb Ctrl register defined by Kirin; > + "phy": apb PHY register defined by Kirin; > + "config": PCIe configuration space registers. > +- reset-gpio: The gpio to generate PCIe perst assert and deassert signal. > + > +Optional properties: > + > +Example based on kirin960: > + > + pcie@f4000000 { > + compatible = "hisilicon,kirin-pcie"; > + reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>, > + <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>; > + reg-names = "dbi","apb","phy", "config"; > + bus-range = <0x0 0x1>; > + #address-cells = <3>; > + #size-cells = <2>; > + device_type = "pci"; > + ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>; > + num-lanes = <1>; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0xf800 0 0 7>; > + interrupt-map = <0x0 0 0 2 &gic 0 0 0 283 4>, Please indent consistently (above line uses tabs, most others use spaces). Also, please line up the cells. > + <0x0 0 0 3 &gic 0 0 0 284 4>, > + <0x0 0 0 4 &gic 0 0 0 285 4>; > + clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, > + <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, > + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, > + <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, > + <&crg_ctrl HI3660_ACLK_GATE_PCIE>; > + clock-names = "pcie_phy_ref", "pcie_aux", > + "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk"; > + reset-gpio = <&gpio11 1 0 >; > + }; > -- > 2.11.GIT >
diff --git a/Documentation/devicetree/bindings/pci/kirin-pcie.txt b/Documentation/devicetree/bindings/pci/kirin-pcie.txt new file mode 100644 index 000000000000..ba6f1bd191f5 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/kirin-pcie.txt @@ -0,0 +1,49 @@ +HiSilicon Kirin SoCs PCIe host DT description + +Kirin PCIe host controller is based on Designware PCI core. +It shares common functions with PCIe Designware core driver +and inherits common properties defined in +Documentation/devicetree/bindings/pci/designware-pci.txt. + +Additional properties are described here: + +Required properties +- compatible: + "hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC +- reg: Should contain rc_dbi, apb, phy, config registers location and length. +- reg-names: Must include the following entries: + "dbi": controller configuration registers; + "apb": apb Ctrl register defined by Kirin; + "phy": apb PHY register defined by Kirin; + "config": PCIe configuration space registers. +- reset-gpio: The gpio to generate PCIe perst assert and deassert signal. + +Optional properties: + +Example based on kirin960: + + pcie@f4000000 { + compatible = "hisilicon,kirin-pcie"; + reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>, + <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>; + reg-names = "dbi","apb","phy", "config"; + bus-range = <0x0 0x1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>; + num-lanes = <1>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0x0 0 0 2 &gic 0 0 0 283 4>, + <0x0 0 0 3 &gic 0 0 0 284 4>, + <0x0 0 0 4 &gic 0 0 0 285 4>; + clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, + <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3660_ACLK_GATE_PCIE>; + clock-names = "pcie_phy_ref", "pcie_aux", + "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk"; + reset-gpio = <&gpio11 1 0 >; + };
Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com> --- .../devicetree/bindings/pci/kirin-pcie.txt | 49 ++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt