| Message ID | 1496398017-6487-3-git-send-email-thomas.petazzoni@free-electrons.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Jun 02, 2017 at 12:06:53PM +0200, Thomas Petazzoni wrote: > This commit adds the Device Tree binding documentation for the Marvell > ICU interrupt controller, which collects wired interrupts from the > devices located into the CP110 hardware block of Marvell Armada 7K/8K, > and converts them into SPI interrupts in the GIC located in the AP > hardware block, using the GICP extension. > > Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> > --- > .../bindings/interrupt-controller/marvell,icu.txt | 54 ++++++++++++++++++++++ > 1 file changed, 54 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt > new file mode 100644 > index 0000000..3e7954c > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt > @@ -0,0 +1,54 @@ > +Marvell ICU Interrupt Controller > +-------------------------------- > + > +The Marvell ICU (Interrupt Consolidation Unit) controller is > +responsible for collecting all wired-interrupt sources in the CP and > +communicating them to the GIC in the AP, the unit translates interrupt > +requests on input wires to MSG memory mapped transactions to the GIC. > + > +Required properties: > + > +- compatible: Should be "marvell,cp110-icu" > + > +- reg: Should contain ICU registers location and length. > + > +- #interrupt-cells: Specifies the number of cells needed to encode an > + interrupt source. The value shall be 3. > + > + The 1st cell is the group type of the ICU interrupt. Possible group > + types are: > + > + ICU_GRP_NSR (0x0) : Shared peripheral interrupt, non-secure > + ICU_GRP_SR (0x1) : Shared peripheral interrupt, secure > + ICU_GRP_SEI (0x4) : System error interrupt > + ICU_GRP_REI (0x5) : RAM error interrupt > + > + The 2nd cell is the index of the interrupt in the ICU unit. > + > + The 3rd cell is the type of the interrupt. See arm,gic.txt for > + details. > + > +- interrupt-controller: Identifies the node as an interrupt > + controller. > + > +- interrupt-parent: Indicates the node of the parent interrupt > + controller. Should be pointer to the GIC. > + > +- gicp: Should point to the GICP controller, the GIC extension that > + allows to trigger interrupts using MSG memory mapped transactions. > + > +Example: > + > +icu: interrupt-controller@1e0000 { > + compatible = "marvell,cp110-icu"; > + reg = <0x1e0000 0x10>; > + #interrupt-cells = <3>; > + interrupt-controller; > + interrupt-parent = <&gic>; If you have a parent, then you should have some interrupts. I guess that would be your ranges property? I suppose that is fine. > + marvell,gicp = <&gicp>; > +}; > + > +usb3h0: usb3@500000 { > + interrupt-parent = <&icu>; > + interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>; > +}; > -- > 2.7.4 >
Hello, On Wed, 7 Jun 2017 17:33:17 -0500, Rob Herring wrote: > > +Example: > > + > > +icu: interrupt-controller@1e0000 { > > + compatible = "marvell,cp110-icu"; > > + reg = <0x1e0000 0x10>; > > + #interrupt-cells = <3>; > > + interrupt-controller; > > + interrupt-parent = <&gic>; > > If you have a parent, then you should have some interrupts. I guess that > would be your ranges property? I suppose that is fine. The ranges of interrupts available is defined by the gicp node. Indeed, as explained in the cover letter: - We have one GICP in the SoC, providing a number of GIC SPI interrupts - We have one ICU per CP in the SoC. So for example in the Armada 8K, we have two CPs, and therefore two ICUs. So the range of available GIC SPI interrupts it not associated to each ICU, it's a global range of GIC SPI interrupts: each can freely be allocated by any of the ICUs in the system. Best regards, Thomas
On Thu, Jun 08, 2017 at 02:12:02PM +0200, Thomas Petazzoni wrote: > Hello, > > On Wed, 7 Jun 2017 17:33:17 -0500, Rob Herring wrote: > > > > +Example: > > > + > > > +icu: interrupt-controller@1e0000 { > > > + compatible = "marvell,cp110-icu"; > > > + reg = <0x1e0000 0x10>; > > > + #interrupt-cells = <3>; > > > + interrupt-controller; > > > + interrupt-parent = <&gic>; > > > > If you have a parent, then you should have some interrupts. I guess that > > would be your ranges property? I suppose that is fine. > > The ranges of interrupts available is defined by the gicp node. Indeed, > as explained in the cover letter: > > - We have one GICP in the SoC, providing a number of GIC SPI interrupts > > - We have one ICU per CP in the SoC. So for example in the Armada 8K, > we have two CPs, and therefore two ICUs. > > So the range of available GIC SPI interrupts it not associated to each > ICU, it's a global range of GIC SPI interrupts: each can freely be > allocated by any of the ICUs in the system. Okay, I guess I have no issues with this one. Acked-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt new file mode 100644 index 0000000..3e7954c --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt @@ -0,0 +1,54 @@ +Marvell ICU Interrupt Controller +-------------------------------- + +The Marvell ICU (Interrupt Consolidation Unit) controller is +responsible for collecting all wired-interrupt sources in the CP and +communicating them to the GIC in the AP, the unit translates interrupt +requests on input wires to MSG memory mapped transactions to the GIC. + +Required properties: + +- compatible: Should be "marvell,cp110-icu" + +- reg: Should contain ICU registers location and length. + +- #interrupt-cells: Specifies the number of cells needed to encode an + interrupt source. The value shall be 3. + + The 1st cell is the group type of the ICU interrupt. Possible group + types are: + + ICU_GRP_NSR (0x0) : Shared peripheral interrupt, non-secure + ICU_GRP_SR (0x1) : Shared peripheral interrupt, secure + ICU_GRP_SEI (0x4) : System error interrupt + ICU_GRP_REI (0x5) : RAM error interrupt + + The 2nd cell is the index of the interrupt in the ICU unit. + + The 3rd cell is the type of the interrupt. See arm,gic.txt for + details. + +- interrupt-controller: Identifies the node as an interrupt + controller. + +- interrupt-parent: Indicates the node of the parent interrupt + controller. Should be pointer to the GIC. + +- gicp: Should point to the GICP controller, the GIC extension that + allows to trigger interrupts using MSG memory mapped transactions. + +Example: + +icu: interrupt-controller@1e0000 { + compatible = "marvell,cp110-icu"; + reg = <0x1e0000 0x10>; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&gic>; + marvell,gicp = <&gicp>; +}; + +usb3h0: usb3@500000 { + interrupt-parent = <&icu>; + interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>; +};
This commit adds the Device Tree binding documentation for the Marvell ICU interrupt controller, which collects wired interrupts from the devices located into the CP110 hardware block of Marvell Armada 7K/8K, and converts them into SPI interrupts in the GIC located in the AP hardware block, using the GICP extension. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> --- .../bindings/interrupt-controller/marvell,icu.txt | 54 ++++++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt