| Message ID | 1496398017-6487-2-git-send-email-thomas.petazzoni@free-electrons.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Jun 02, 2017 at 12:06:52PM +0200, Thomas Petazzoni wrote: > This commit adds the Device Tree binding documentation for the Marvell > GICP, an extension to the GIC that allows to trigger GIC SPI interrupts > using memory transactions. It is used by the ICU unit in the Marvell > CP110 block to turn wired interrupts inside the CP into SPI interrupts > at the GIC level in the AP. Sounds like an MSI block? > Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> > --- > .../bindings/interrupt-controller/marvell,gicp.txt | 24 ++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt > new file mode 100644 > index 0000000..3fc36963 > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt > @@ -0,0 +1,24 @@ > +Marvell GICP Controller > +----------------------- > + > +GICP is a Marvell extension of the GIC that allows to trigger GIC SPI > +interrupts by doing a memory transaction. It is used by the ICU > +located in the Marvell CP110 to turn wired interrupts inside the CP > +into GIC SPI interrupts. > + > +Required properties: > + > +- compatible: Must be "marvell,ap806-gicp" > + > +- reg: Must be the address and size of the GICP SPI registers > + > +- marvell,spi-ranges: tuples of GIC SPI interrupts ranges available > + for this GICP These are base+size? > + > +Example: > + > +gicp_spi: gicp-spi@3f0040 { > + compatible = "marvell,ap806-gicp"; > + reg = <0x3f0040 0x10>; > + marvell,spi-ranges = <64 64>, <288 64>; > +}; > -- > 2.7.4 >
On 07/06/17 23:24, Rob Herring wrote: > On Fri, Jun 02, 2017 at 12:06:52PM +0200, Thomas Petazzoni wrote: >> This commit adds the Device Tree binding documentation for the Marvell >> GICP, an extension to the GIC that allows to trigger GIC SPI interrupts >> using memory transactions. It is used by the ICU unit in the Marvell >> CP110 block to turn wired interrupts inside the CP into SPI interrupts >> at the GIC level in the AP. > > Sounds like an MSI block? Almost. It also allows to deal with level interrupts, which a classic MSI controller cannot manage. This looks like it has been lifted from the GICv3 spec, which offers the exact same mechanism for SPIs. Thanks, M.
Hello, On Wed, 7 Jun 2017 17:24:20 -0500, Rob Herring wrote: > On Fri, Jun 02, 2017 at 12:06:52PM +0200, Thomas Petazzoni wrote: > > This commit adds the Device Tree binding documentation for the Marvell > > GICP, an extension to the GIC that allows to trigger GIC SPI interrupts > > using memory transactions. It is used by the ICU unit in the Marvell > > CP110 block to turn wired interrupts inside the CP into SPI interrupts > > at the GIC level in the AP. > > Sounds like an MSI block? Marc Zyngier answered on this (much better than I could have done). > > +- marvell,spi-ranges: tuples of GIC SPI interrupts ranges available > > + for this GICP > > These are base+size? Correct. Does your question suggest that I should update the binding document to make this explicit? Thanks, Thomas
On Thu, Jun 08, 2017 at 02:10:23PM +0200, Thomas Petazzoni wrote: > Hello, > > On Wed, 7 Jun 2017 17:24:20 -0500, Rob Herring wrote: > > On Fri, Jun 02, 2017 at 12:06:52PM +0200, Thomas Petazzoni wrote: > > > This commit adds the Device Tree binding documentation for the Marvell > > > GICP, an extension to the GIC that allows to trigger GIC SPI interrupts > > > using memory transactions. It is used by the ICU unit in the Marvell > > > CP110 block to turn wired interrupts inside the CP into SPI interrupts > > > at the GIC level in the AP. > > > > Sounds like an MSI block? > > Marc Zyngier answered on this (much better than I could have done). > > > > +- marvell,spi-ranges: tuples of GIC SPI interrupts ranges available > > > + for this GICP > > > > These are base+size? > > Correct. Does your question suggest that I should update the binding > document to make this explicit? Yes, please. Rob
diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt new file mode 100644 index 0000000..3fc36963 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt @@ -0,0 +1,24 @@ +Marvell GICP Controller +----------------------- + +GICP is a Marvell extension of the GIC that allows to trigger GIC SPI +interrupts by doing a memory transaction. It is used by the ICU +located in the Marvell CP110 to turn wired interrupts inside the CP +into GIC SPI interrupts. + +Required properties: + +- compatible: Must be "marvell,ap806-gicp" + +- reg: Must be the address and size of the GICP SPI registers + +- marvell,spi-ranges: tuples of GIC SPI interrupts ranges available + for this GICP + +Example: + +gicp_spi: gicp-spi@3f0040 { + compatible = "marvell,ap806-gicp"; + reg = <0x3f0040 0x10>; + marvell,spi-ranges = <64 64>, <288 64>; +};
This commit adds the Device Tree binding documentation for the Marvell GICP, an extension to the GIC that allows to trigger GIC SPI interrupts using memory transactions. It is used by the ICU unit in the Marvell CP110 block to turn wired interrupts inside the CP into SPI interrupts at the GIC level in the AP. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> --- .../bindings/interrupt-controller/marvell,gicp.txt | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt