| Message ID | 20170531071852.12422-6-clabbe.montjoie@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 31/05/17 08:18, Corentin Labbe wrote: > The dwmac-sun8i is a heavy hacked version of stmmac hardware by > allwinner. > In fact the only common part is the descriptor management and the first > register function. Hi, I know I am a bit late with this, but while adapting the U-Boot driver to the new binding I was wondering about the internal PHY detection: > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c > new file mode 100644 > index 000000000000..1a6bfe6c958f > --- /dev/null > +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c > @@ -0,0 +1,990 @@ .... > +static int sun8i_dwmac_probe(struct platform_device *pdev) > +{ > + struct plat_stmmacenet_data *plat_dat; > + struct stmmac_resources stmmac_res; > + struct sunxi_priv_data *gmac; > + struct device *dev = &pdev->dev; > + int ret; > + > + ret = stmmac_get_platform_resources(pdev, &stmmac_res); > + if (ret) > + return ret; > + > + plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); > + if (IS_ERR(plat_dat)) > + return PTR_ERR(plat_dat); > + > + gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL); > + if (!gmac) > + return -ENOMEM; > + > + gmac->variant = of_device_get_match_data(&pdev->dev); > + if (!gmac->variant) { > + dev_err(&pdev->dev, "Missing dwmac-sun8i variant\n"); > + return -EINVAL; > + } > + > + gmac->tx_clk = devm_clk_get(dev, "stmmaceth"); > + if (IS_ERR(gmac->tx_clk)) { > + dev_err(dev, "Could not get TX clock\n"); > + return PTR_ERR(gmac->tx_clk); > + } > + > + /* Optional regulator for PHY */ > + gmac->regulator = devm_regulator_get_optional(dev, "phy"); > + if (IS_ERR(gmac->regulator)) { > + if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER) > + return -EPROBE_DEFER; > + dev_info(dev, "No regulator found\n"); > + gmac->regulator = NULL; > + } > + > + gmac->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, > + "syscon"); > + if (IS_ERR(gmac->regmap)) { > + ret = PTR_ERR(gmac->regmap); > + dev_err(&pdev->dev, "Unable to map syscon: %d\n", ret); > + return ret; > + } > + > + plat_dat->interface = of_get_phy_mode(dev->of_node); > + if (plat_dat->interface == gmac->variant->internal_phy) { > + dev_info(&pdev->dev, "Will use internal PHY\n"); So here you seem to deduce the usage of the internal PHY by the PHY interface specified in the DT (MII = internal, RGMII = external). I think I raised this question before, but isn't it perfectly legal for a board to use MII with an external PHY even on those SoCs that feature an internal PHY? On the first glance that does not make too much sense, but apart from not being the correct binding to describe all of the SoCs features I see two scenarios: 1) A board vendor might choose to not use the internal PHY because it has bugs, lacks features (configurability) or has other issues. For instance I have heard reports that the internal PHY makes the SoC go rather hot, possibly limiting the CPU frequency. By using an external MII PHY (which are still cheaper than RGMII PHYs) this can be avoided. 2) A PHY does not necessarily need to be directly connected to magnetics. Indeed quite some boards use (RG)MII to connect to a switch IC or some other network circuitry, for instance fibre connectors. So I was wondering if we would need an explicit: allwinner,use-internal-phy; boolean DT property to signal the usage of the internal PHY? Alternatively we could go with the negative version: allwinner,disable-internal-phy; Or what about introducing a new "allwinner,internal-mii-phy" compatible string for the *PHY* node and use that? I just want to avoid that we introduce a binding that causes us headaches later. I think we can still fix this with a followup patch before the driver and its binding hit a release kernel. Cheers, Andre. > + gmac->use_internal_phy = true; > + gmac->ephy_clk = of_clk_get(plat_dat->phy_node, 0); > + if (IS_ERR(gmac->ephy_clk)) { > + ret = PTR_ERR(gmac->ephy_clk); > + dev_err(&pdev->dev, "Cannot get EPHY clock: %d\n", ret); > + return -EINVAL; > + } > + > + gmac->rst_ephy = of_reset_control_get(plat_dat->phy_node, NULL); > + if (IS_ERR(gmac->rst_ephy)) { > + ret = PTR_ERR(gmac->rst_ephy); > + if (ret == -EPROBE_DEFER) > + return ret; > + dev_err(&pdev->dev, "No EPHY reset control found %d\n", > + ret); > + return -EINVAL; > + } > + } else { > + dev_info(&pdev->dev, "Will use external PHY\n"); > + gmac->use_internal_phy = false; > + } > + > + /* platform data specifying hardware features and callbacks. > + * hardware features were copied from Allwinner drivers. > + */ > + plat_dat->rx_coe = STMMAC_RX_COE_TYPE2; > + plat_dat->tx_coe = 1; > + plat_dat->has_sun8i = true; > + plat_dat->bsp_priv = gmac; > + plat_dat->init = sun8i_dwmac_init; > + plat_dat->exit = sun8i_dwmac_exit; > + plat_dat->setup = sun8i_dwmac_setup; > + > + ret = sun8i_dwmac_init(pdev, plat_dat->bsp_priv); > + if (ret) > + return ret; > + > + ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); > + if (ret) > + sun8i_dwmac_exit(pdev, plat_dat->bsp_priv); > + > + return ret; > +} > + > +static const struct of_device_id sun8i_dwmac_match[] = { > + { .compatible = "allwinner,sun8i-h3-emac", > + .data = &emac_variant_h3 }, > + { .compatible = "allwinner,sun8i-a83t-emac", > + .data = &emac_variant_a83t }, > + { .compatible = "allwinner,sun50i-a64-emac", > + .data = &emac_variant_a64 }, > + { } > +}; > +MODULE_DEVICE_TABLE(of, sun8i_dwmac_match); > + > +static struct platform_driver sun8i_dwmac_driver = { > + .probe = sun8i_dwmac_probe, > + .remove = stmmac_pltfr_remove, > + .driver = { > + .name = "dwmac-sun8i", > + .pm = &stmmac_pltfr_pm_ops, > + .of_match_table = sun8i_dwmac_match, > + }, > +}; > +module_platform_driver(sun8i_dwmac_driver); > + > +MODULE_AUTHOR("Corentin Labbe <clabbe.montjoie@gmail.com>"); > +MODULE_DESCRIPTION("Allwinner sun8i DWMAC specific glue layer"); > +MODULE_LICENSE("GPL"); > diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c > index c80c9c3b67db..68a188e74c54 100644 > --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c > +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c > @@ -235,6 +235,17 @@ static void stmmac_clk_csr_set(struct stmmac_priv *priv) > else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) > priv->clk_csr = STMMAC_CSR_250_300M; > } > + > + if (priv->plat->has_sun8i) { > + if (clk_rate > 160000000) > + priv->clk_csr = 0x03; > + else if (clk_rate > 80000000) > + priv->clk_csr = 0x02; > + else if (clk_rate > 40000000) > + priv->clk_csr = 0x01; > + else > + priv->clk_csr = 0; > + } > } > > static void print_pkt(unsigned char *buf, int len) > @@ -3955,6 +3966,10 @@ static int stmmac_hw_init(struct stmmac_priv *priv) > > priv->hw = mac; > > + /* dwmac-sun8i only work in chain mode */ > + if (priv->plat->has_sun8i) > + chain_mode = 1; > + > /* To use the chained or ring mode */ > if (priv->synopsys_id >= DWMAC_CORE_4_00) { > priv->hw->mode = &dwmac4_ring_mode_ops; > diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c > index 7fc3a1ef395a..3840529344ed 100644 > --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c > +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c > @@ -309,6 +309,12 @@ static int stmmac_dt_phy(struct plat_stmmacenet_data *plat, > struct device_node *np, struct device *dev) > { > bool mdio = true; > + static const struct of_device_id need_mdio_ids[] = { > + { .compatible = "snps,dwc-qos-ethernet-4.10" }, > + { .compatible = "allwinner,sun8i-a83t-emac" }, > + { .compatible = "allwinner,sun8i-h3-emac" }, > + { .compatible = "allwinner,sun50i-a64-emac" }, > + }; > > /* If phy-handle property is passed from DT, use it as the PHY */ > plat->phy_node = of_parse_phandle(np, "phy-handle", 0); > @@ -325,8 +331,7 @@ static int stmmac_dt_phy(struct plat_stmmacenet_data *plat, > mdio = false; > } > > - /* exception for dwmac-dwc-qos-eth glue logic */ > - if (of_device_is_compatible(np, "snps,dwc-qos-ethernet-4.10")) { > + if (of_match_node(need_mdio_ids, np)) { > plat->mdio_node = of_get_child_by_name(np, "mdio"); > } else { > /** > diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h > index 8bb550bca96d..108739ff9223 100644 > --- a/include/linux/stmmac.h > +++ b/include/linux/stmmac.h > @@ -186,6 +186,7 @@ struct plat_stmmacenet_data { > struct reset_control *stmmac_rst; > struct stmmac_axi *axi; > int has_gmac4; > + bool has_sun8i; > bool tso_en; > int mac_port_sel_speed; > bool en_tx_lpi_clockgating; >
On Mon, Jun 26, 2017 at 01:18:23AM +0100, André Przywara wrote: > On 31/05/17 08:18, Corentin Labbe wrote: > > The dwmac-sun8i is a heavy hacked version of stmmac hardware by > > allwinner. > > In fact the only common part is the descriptor management and the first > > register function. > > Hi, > > I know I am a bit late with this, but while adapting the U-Boot driver > to the new binding I was wondering about the internal PHY detection: > > > So here you seem to deduce the usage of the internal PHY by the PHY > interface specified in the DT (MII = internal, RGMII = external). > I think I raised this question before, but isn't it perfectly legal for > a board to use MII with an external PHY even on those SoCs that feature > an internal PHY? > On the first glance that does not make too much sense, but apart from > not being the correct binding to describe all of the SoCs features I see > two scenarios: > 1) A board vendor might choose to not use the internal PHY because it > has bugs, lacks features (configurability) or has other issues. For > instance I have heard reports that the internal PHY makes the SoC go > rather hot, possibly limiting the CPU frequency. By using an external > MII PHY (which are still cheaper than RGMII PHYs) this can be avoided. > 2) A PHY does not necessarily need to be directly connected to > magnetics. Indeed quite some boards use (RG)MII to connect to a switch > IC or some other network circuitry, for instance fibre connectors. > > So I was wondering if we would need an explicit: > allwinner,use-internal-phy; > boolean DT property to signal the usage of the internal PHY? > Alternatively we could go with the negative version: > allwinner,disable-internal-phy; > > Or what about introducing a new "allwinner,internal-mii-phy" compatible > string for the *PHY* node and use that? > > I just want to avoid that we introduce a binding that causes us > headaches later. I think we can still fix this with a followup patch > before the driver and its binding hit a release kernel. > > Cheers, > Andre. > I just see some patch, where "phy-mode = internal" is valid. I will try to find a way to use it Regards
On Tue, Jun 27, 2017 at 4:05 PM, Corentin Labbe <clabbe.montjoie@gmail.com> wrote: > On Mon, Jun 26, 2017 at 01:18:23AM +0100, André Przywara wrote: >> On 31/05/17 08:18, Corentin Labbe wrote: >> > The dwmac-sun8i is a heavy hacked version of stmmac hardware by >> > allwinner. >> > In fact the only common part is the descriptor management and the first >> > register function. >> >> Hi, >> >> I know I am a bit late with this, but while adapting the U-Boot driver >> to the new binding I was wondering about the internal PHY detection: >> >> >> So here you seem to deduce the usage of the internal PHY by the PHY >> interface specified in the DT (MII = internal, RGMII = external). >> I think I raised this question before, but isn't it perfectly legal for >> a board to use MII with an external PHY even on those SoCs that feature >> an internal PHY? >> On the first glance that does not make too much sense, but apart from >> not being the correct binding to describe all of the SoCs features I see >> two scenarios: >> 1) A board vendor might choose to not use the internal PHY because it >> has bugs, lacks features (configurability) or has other issues. For >> instance I have heard reports that the internal PHY makes the SoC go >> rather hot, possibly limiting the CPU frequency. By using an external >> MII PHY (which are still cheaper than RGMII PHYs) this can be avoided. >> 2) A PHY does not necessarily need to be directly connected to >> magnetics. Indeed quite some boards use (RG)MII to connect to a switch >> IC or some other network circuitry, for instance fibre connectors. >> >> So I was wondering if we would need an explicit: >> allwinner,use-internal-phy; >> boolean DT property to signal the usage of the internal PHY? >> Alternatively we could go with the negative version: >> allwinner,disable-internal-phy; >> >> Or what about introducing a new "allwinner,internal-mii-phy" compatible >> string for the *PHY* node and use that? >> >> I just want to avoid that we introduce a binding that causes us >> headaches later. I think we can still fix this with a followup patch >> before the driver and its binding hit a release kernel. >> >> Cheers, >> Andre. >> > > I just see some patch, where "phy-mode = internal" is valid. > I will try to find a way to use it Can you provide a link? I'm not a fan of using phy-mode for this. There's no guarantee what mode the internal PHY uses. That's what phy-mode is for. In any case, we should fix this before 4.13 is released. ChenYu
On Tue, Jun 27, 2017 at 04:11:21PM +0800, Chen-Yu Tsai wrote: > On Tue, Jun 27, 2017 at 4:05 PM, Corentin Labbe > <clabbe.montjoie@gmail.com> wrote: > > On Mon, Jun 26, 2017 at 01:18:23AM +0100, André Przywara wrote: > >> On 31/05/17 08:18, Corentin Labbe wrote: > >> > The dwmac-sun8i is a heavy hacked version of stmmac hardware by > >> > allwinner. > >> > In fact the only common part is the descriptor management and the first > >> > register function. > >> > >> Hi, > >> > >> I know I am a bit late with this, but while adapting the U-Boot driver > >> to the new binding I was wondering about the internal PHY detection: > >> > >> > >> So here you seem to deduce the usage of the internal PHY by the PHY > >> interface specified in the DT (MII = internal, RGMII = external). > >> I think I raised this question before, but isn't it perfectly legal for > >> a board to use MII with an external PHY even on those SoCs that feature > >> an internal PHY? > >> On the first glance that does not make too much sense, but apart from > >> not being the correct binding to describe all of the SoCs features I see > >> two scenarios: > >> 1) A board vendor might choose to not use the internal PHY because it > >> has bugs, lacks features (configurability) or has other issues. For > >> instance I have heard reports that the internal PHY makes the SoC go > >> rather hot, possibly limiting the CPU frequency. By using an external > >> MII PHY (which are still cheaper than RGMII PHYs) this can be avoided. > >> 2) A PHY does not necessarily need to be directly connected to > >> magnetics. Indeed quite some boards use (RG)MII to connect to a switch > >> IC or some other network circuitry, for instance fibre connectors. > >> > >> So I was wondering if we would need an explicit: > >> allwinner,use-internal-phy; > >> boolean DT property to signal the usage of the internal PHY? > >> Alternatively we could go with the negative version: > >> allwinner,disable-internal-phy; > >> > >> Or what about introducing a new "allwinner,internal-mii-phy" compatible > >> string for the *PHY* node and use that? > >> > >> I just want to avoid that we introduce a binding that causes us > >> headaches later. I think we can still fix this with a followup patch > >> before the driver and its binding hit a release kernel. > >> > >> Cheers, > >> Andre. > >> > > > > I just see some patch, where "phy-mode = internal" is valid. > > I will try to find a way to use it > > Can you provide a link? https://lkml.org/lkml/2017/6/23/479 > > I'm not a fan of using phy-mode for this. There's no guarantee what > mode the internal PHY uses. That's what phy-mode is for. For each soc the internal PHY mode is know and setted in emac_variant/internal_phy So its not a problem. Patch comming soon
Hi, (CC:ing some people from that Rockchip dmwac series) On 27/06/17 09:21, Corentin Labbe wrote: > On Tue, Jun 27, 2017 at 04:11:21PM +0800, Chen-Yu Tsai wrote: >> On Tue, Jun 27, 2017 at 4:05 PM, Corentin Labbe >> <clabbe.montjoie@gmail.com> wrote: >>> On Mon, Jun 26, 2017 at 01:18:23AM +0100, André Przywara wrote: >>>> On 31/05/17 08:18, Corentin Labbe wrote: >>>>> The dwmac-sun8i is a heavy hacked version of stmmac hardware by >>>>> allwinner. >>>>> In fact the only common part is the descriptor management and the first >>>>> register function. >>>> >>>> Hi, >>>> >>>> I know I am a bit late with this, but while adapting the U-Boot driver >>>> to the new binding I was wondering about the internal PHY detection: >>>> >>>> >>>> So here you seem to deduce the usage of the internal PHY by the PHY >>>> interface specified in the DT (MII = internal, RGMII = external). >>>> I think I raised this question before, but isn't it perfectly legal for >>>> a board to use MII with an external PHY even on those SoCs that feature >>>> an internal PHY? >>>> On the first glance that does not make too much sense, but apart from >>>> not being the correct binding to describe all of the SoCs features I see >>>> two scenarios: >>>> 1) A board vendor might choose to not use the internal PHY because it >>>> has bugs, lacks features (configurability) or has other issues. For >>>> instance I have heard reports that the internal PHY makes the SoC go >>>> rather hot, possibly limiting the CPU frequency. By using an external >>>> MII PHY (which are still cheaper than RGMII PHYs) this can be avoided. >>>> 2) A PHY does not necessarily need to be directly connected to >>>> magnetics. Indeed quite some boards use (RG)MII to connect to a switch >>>> IC or some other network circuitry, for instance fibre connectors. >>>> >>>> So I was wondering if we would need an explicit: >>>> allwinner,use-internal-phy; >>>> boolean DT property to signal the usage of the internal PHY? >>>> Alternatively we could go with the negative version: >>>> allwinner,disable-internal-phy; >>>> >>>> Or what about introducing a new "allwinner,internal-mii-phy" compatible >>>> string for the *PHY* node and use that? >>>> >>>> I just want to avoid that we introduce a binding that causes us >>>> headaches later. I think we can still fix this with a followup patch >>>> before the driver and its binding hit a release kernel. >>>> >>>> Cheers, >>>> Andre. >>>> >>> >>> I just see some patch, where "phy-mode = internal" is valid. >>> I will try to find a way to use it >> >> Can you provide a link? > > https://lkml.org/lkml/2017/6/23/479 > >> >> I'm not a fan of using phy-mode for this. There's no guarantee what >> mode the internal PHY uses. That's what phy-mode is for. I can understand Chen-Yu's concerns, but ... > For each soc the internal PHY mode is know and setted in emac_variant/internal_phy > So its not a problem. that is true as well, at least for now. So while I agree that having a separate property to indicate the usage of the internal PHY would be nice, I am bit tempted to use this easier approach and piggy back on the existing phy-mode property. Are there any insights from the people involved with the Rockchip internal PHY? It is worth to introduce a generic boolean property for an internal PHY? Or shall we actually move this more into the PHY code, introducing new compatibles for the internal Allwinner and Rockchip Ethernet PHYs? Cheers, Andre.
On Tue, Jun 27, 2017 at 10:02:45AM +0100, Andre Przywara wrote: > Hi, > > (CC:ing some people from that Rockchip dmwac series) > > On 27/06/17 09:21, Corentin Labbe wrote: > > On Tue, Jun 27, 2017 at 04:11:21PM +0800, Chen-Yu Tsai wrote: > >> On Tue, Jun 27, 2017 at 4:05 PM, Corentin Labbe > >> <clabbe.montjoie@gmail.com> wrote: > >>> On Mon, Jun 26, 2017 at 01:18:23AM +0100, André Przywara wrote: > >>>> On 31/05/17 08:18, Corentin Labbe wrote: > >>>>> The dwmac-sun8i is a heavy hacked version of stmmac hardware by > >>>>> allwinner. > >>>>> In fact the only common part is the descriptor management and the first > >>>>> register function. > >>>> > >>>> Hi, > >>>> > >>>> I know I am a bit late with this, but while adapting the U-Boot driver > >>>> to the new binding I was wondering about the internal PHY detection: > >>>> > >>>> > >>>> So here you seem to deduce the usage of the internal PHY by the PHY > >>>> interface specified in the DT (MII = internal, RGMII = external). > >>>> I think I raised this question before, but isn't it perfectly legal for > >>>> a board to use MII with an external PHY even on those SoCs that feature > >>>> an internal PHY? > >>>> On the first glance that does not make too much sense, but apart from > >>>> not being the correct binding to describe all of the SoCs features I see > >>>> two scenarios: > >>>> 1) A board vendor might choose to not use the internal PHY because it > >>>> has bugs, lacks features (configurability) or has other issues. For > >>>> instance I have heard reports that the internal PHY makes the SoC go > >>>> rather hot, possibly limiting the CPU frequency. By using an external > >>>> MII PHY (which are still cheaper than RGMII PHYs) this can be avoided. > >>>> 2) A PHY does not necessarily need to be directly connected to > >>>> magnetics. Indeed quite some boards use (RG)MII to connect to a switch > >>>> IC or some other network circuitry, for instance fibre connectors. > >>>> > >>>> So I was wondering if we would need an explicit: > >>>> allwinner,use-internal-phy; > >>>> boolean DT property to signal the usage of the internal PHY? > >>>> Alternatively we could go with the negative version: > >>>> allwinner,disable-internal-phy; > >>>> > >>>> Or what about introducing a new "allwinner,internal-mii-phy" compatible > >>>> string for the *PHY* node and use that? > >>>> > >>>> I just want to avoid that we introduce a binding that causes us > >>>> headaches later. I think we can still fix this with a followup patch > >>>> before the driver and its binding hit a release kernel. > >>>> > >>>> Cheers, > >>>> Andre. > >>>> > >>> > >>> I just see some patch, where "phy-mode = internal" is valid. > >>> I will try to find a way to use it > >> > >> Can you provide a link? > > > > https://lkml.org/lkml/2017/6/23/479 > > > >> > >> I'm not a fan of using phy-mode for this. There's no guarantee what > >> mode the internal PHY uses. That's what phy-mode is for. > > I can understand Chen-Yu's concerns, but ... > > > For each soc the internal PHY mode is know and setted in emac_variant/internal_phy > > So its not a problem. > > that is true as well, at least for now. > > So while I agree that having a separate property to indicate the usage > of the internal PHY would be nice, I am bit tempted to use this easier > approach and piggy back on the existing phy-mode property. We're trying to fix an issue that works for now too. If we want to consider future weird cases, then we must consider all of them. And the phy mode changing is definitely not really far fetched. I agree with Chen-Yu, and I really feel like the compatible solution you suggested would cover both your concerns, and ours. Maxime
On Tue, Jun 27, 2017 at 5:41 PM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > On Tue, Jun 27, 2017 at 10:02:45AM +0100, Andre Przywara wrote: >> Hi, >> >> (CC:ing some people from that Rockchip dmwac series) >> >> On 27/06/17 09:21, Corentin Labbe wrote: >> > On Tue, Jun 27, 2017 at 04:11:21PM +0800, Chen-Yu Tsai wrote: >> >> On Tue, Jun 27, 2017 at 4:05 PM, Corentin Labbe >> >> <clabbe.montjoie@gmail.com> wrote: >> >>> On Mon, Jun 26, 2017 at 01:18:23AM +0100, André Przywara wrote: >> >>>> On 31/05/17 08:18, Corentin Labbe wrote: >> >>>>> The dwmac-sun8i is a heavy hacked version of stmmac hardware by >> >>>>> allwinner. >> >>>>> In fact the only common part is the descriptor management and the first >> >>>>> register function. >> >>>> >> >>>> Hi, >> >>>> >> >>>> I know I am a bit late with this, but while adapting the U-Boot driver >> >>>> to the new binding I was wondering about the internal PHY detection: >> >>>> >> >>>> >> >>>> So here you seem to deduce the usage of the internal PHY by the PHY >> >>>> interface specified in the DT (MII = internal, RGMII = external). >> >>>> I think I raised this question before, but isn't it perfectly legal for >> >>>> a board to use MII with an external PHY even on those SoCs that feature >> >>>> an internal PHY? >> >>>> On the first glance that does not make too much sense, but apart from >> >>>> not being the correct binding to describe all of the SoCs features I see >> >>>> two scenarios: >> >>>> 1) A board vendor might choose to not use the internal PHY because it >> >>>> has bugs, lacks features (configurability) or has other issues. For >> >>>> instance I have heard reports that the internal PHY makes the SoC go >> >>>> rather hot, possibly limiting the CPU frequency. By using an external >> >>>> MII PHY (which are still cheaper than RGMII PHYs) this can be avoided. >> >>>> 2) A PHY does not necessarily need to be directly connected to >> >>>> magnetics. Indeed quite some boards use (RG)MII to connect to a switch >> >>>> IC or some other network circuitry, for instance fibre connectors. >> >>>> >> >>>> So I was wondering if we would need an explicit: >> >>>> allwinner,use-internal-phy; >> >>>> boolean DT property to signal the usage of the internal PHY? >> >>>> Alternatively we could go with the negative version: >> >>>> allwinner,disable-internal-phy; >> >>>> >> >>>> Or what about introducing a new "allwinner,internal-mii-phy" compatible >> >>>> string for the *PHY* node and use that? >> >>>> >> >>>> I just want to avoid that we introduce a binding that causes us >> >>>> headaches later. I think we can still fix this with a followup patch >> >>>> before the driver and its binding hit a release kernel. >> >>>> >> >>>> Cheers, >> >>>> Andre. >> >>>> >> >>> >> >>> I just see some patch, where "phy-mode = internal" is valid. >> >>> I will try to find a way to use it >> >> >> >> Can you provide a link? >> > >> > https://lkml.org/lkml/2017/6/23/479 >> > >> >> >> >> I'm not a fan of using phy-mode for this. There's no guarantee what >> >> mode the internal PHY uses. That's what phy-mode is for. >> >> I can understand Chen-Yu's concerns, but ... >> >> > For each soc the internal PHY mode is know and setted in emac_variant/internal_phy >> > So its not a problem. >> >> that is true as well, at least for now. >> >> So while I agree that having a separate property to indicate the usage >> of the internal PHY would be nice, I am bit tempted to use this easier >> approach and piggy back on the existing phy-mode property. > > We're trying to fix an issue that works for now too. > > If we want to consider future weird cases, then we must consider all > of them. And the phy mode changing is definitely not really far > fetched. I guess the issue is whether it's likely that the vendor puts 2 internal PHYs in one SoC, and they use different modes and can be switched around. Otherwise it's fixed for a given SoC, and we can just handle that with the per-SoC GMAC compatible. Maybe Florian could tell us if this was one of the intended use cases for the "internal" phy mode. As for Rockchip, AFAIK they have 2 MACs, one is connected to the internal PHY, while the other is connected to the external interface, and there is no muxing involved, unlike Allwinner's solution. > I agree with Chen-Yu, and I really feel like the compatible solution > you suggested would cover both your concerns, and ours. If using a PHY compatible is the solution, we could just use the "ethernet-phy-idAAAA.BBBB" style one, and put in the bogus ID that Allwinner used. Care must be taken to put this at the board level for boards using the internal PHY, or we'd have to delete or override the property in all other boards. Ideally I think the internal PHY device node should _not_ be in the SoC level .dtsi file. If we select the external interface, then there's no connection to the internal PHY, and that device node becomes unusable and bogus. This is something I think should be fixed regardless of the phy-mode discussion above. ChenYu
Hi, On 27/06/17 10:41, Maxime Ripard wrote: > On Tue, Jun 27, 2017 at 10:02:45AM +0100, Andre Przywara wrote: >> Hi, >> >> (CC:ing some people from that Rockchip dmwac series) >> >> On 27/06/17 09:21, Corentin Labbe wrote: >>> On Tue, Jun 27, 2017 at 04:11:21PM +0800, Chen-Yu Tsai wrote: >>>> On Tue, Jun 27, 2017 at 4:05 PM, Corentin Labbe >>>> <clabbe.montjoie@gmail.com> wrote: >>>>> On Mon, Jun 26, 2017 at 01:18:23AM +0100, André Przywara wrote: >>>>>> On 31/05/17 08:18, Corentin Labbe wrote: >>>>>>> The dwmac-sun8i is a heavy hacked version of stmmac hardware by >>>>>>> allwinner. >>>>>>> In fact the only common part is the descriptor management and the first >>>>>>> register function. >>>>>> >>>>>> Hi, >>>>>> >>>>>> I know I am a bit late with this, but while adapting the U-Boot driver >>>>>> to the new binding I was wondering about the internal PHY detection: >>>>>> >>>>>> >>>>>> So here you seem to deduce the usage of the internal PHY by the PHY >>>>>> interface specified in the DT (MII = internal, RGMII = external). >>>>>> I think I raised this question before, but isn't it perfectly legal for >>>>>> a board to use MII with an external PHY even on those SoCs that feature >>>>>> an internal PHY? >>>>>> On the first glance that does not make too much sense, but apart from >>>>>> not being the correct binding to describe all of the SoCs features I see >>>>>> two scenarios: >>>>>> 1) A board vendor might choose to not use the internal PHY because it >>>>>> has bugs, lacks features (configurability) or has other issues. For >>>>>> instance I have heard reports that the internal PHY makes the SoC go >>>>>> rather hot, possibly limiting the CPU frequency. By using an external >>>>>> MII PHY (which are still cheaper than RGMII PHYs) this can be avoided. >>>>>> 2) A PHY does not necessarily need to be directly connected to >>>>>> magnetics. Indeed quite some boards use (RG)MII to connect to a switch >>>>>> IC or some other network circuitry, for instance fibre connectors. >>>>>> >>>>>> So I was wondering if we would need an explicit: >>>>>> allwinner,use-internal-phy; >>>>>> boolean DT property to signal the usage of the internal PHY? >>>>>> Alternatively we could go with the negative version: >>>>>> allwinner,disable-internal-phy; >>>>>> >>>>>> Or what about introducing a new "allwinner,internal-mii-phy" compatible >>>>>> string for the *PHY* node and use that? >>>>>> >>>>>> I just want to avoid that we introduce a binding that causes us >>>>>> headaches later. I think we can still fix this with a followup patch >>>>>> before the driver and its binding hit a release kernel. >>>>>> >>>>>> Cheers, >>>>>> Andre. >>>>>> >>>>> >>>>> I just see some patch, where "phy-mode = internal" is valid. >>>>> I will try to find a way to use it >>>> >>>> Can you provide a link? >>> >>> https://lkml.org/lkml/2017/6/23/479 >>> >>>> >>>> I'm not a fan of using phy-mode for this. There's no guarantee what >>>> mode the internal PHY uses. That's what phy-mode is for. >> >> I can understand Chen-Yu's concerns, but ... >> >>> For each soc the internal PHY mode is know and setted in emac_variant/internal_phy >>> So its not a problem. >> >> that is true as well, at least for now. >> >> So while I agree that having a separate property to indicate the usage >> of the internal PHY would be nice, I am bit tempted to use this easier >> approach and piggy back on the existing phy-mode property. > > We're trying to fix an issue that works for now too. > > If we want to consider future weird cases, then we must consider all > of them. And the phy mode changing is definitely not really far > fetched. > > I agree with Chen-Yu, and I really feel like the compatible solution > you suggested would cover both your concerns, and ours. So something like this? emac: emac@1c30000 { compatible = "allwinner,sun8i-h3-emac"; ... phy-mode = "mii"; phy-handle = <&int_mii_phy>; ... mdio: mdio { #address-cells = <1>; #size-cells = <0>; int_mii_phy: ethernet-phy@1 { compatible = "allwinner,sun8i-h3-ephy"; syscon = <&syscon>; reg = <1>; clocks = <&ccu CLK_BUS_EPHY>; resets = <&ccu RST_BUS_EPHY>; }; }; }; And then move the internal-PHY setup code into a separate PHY driver? That looks like the architecturally best solution to me, but is probably also a bit involved since it would require a separate PHY driver. Or can we make it simpler, but still use this binding? Cheers, Andre.
于 2017年6月27日 GMT+08:00 下午6:11:47, Chen-Yu Tsai <wens@csie.org> 写到: >On Tue, Jun 27, 2017 at 5:41 PM, Maxime Ripard ><maxime.ripard@free-electrons.com> wrote: >> On Tue, Jun 27, 2017 at 10:02:45AM +0100, Andre Przywara wrote: >>> Hi, >>> >>> (CC:ing some people from that Rockchip dmwac series) >>> >>> On 27/06/17 09:21, Corentin Labbe wrote: >>> > On Tue, Jun 27, 2017 at 04:11:21PM +0800, Chen-Yu Tsai wrote: >>> >> On Tue, Jun 27, 2017 at 4:05 PM, Corentin Labbe >>> >> <clabbe.montjoie@gmail.com> wrote: >>> >>> On Mon, Jun 26, 2017 at 01:18:23AM +0100, André Przywara wrote: >>> >>>> On 31/05/17 08:18, Corentin Labbe wrote: >>> >>>>> The dwmac-sun8i is a heavy hacked version of stmmac hardware >by >>> >>>>> allwinner. >>> >>>>> In fact the only common part is the descriptor management and >the first >>> >>>>> register function. >>> >>>> >>> >>>> Hi, >>> >>>> >>> >>>> I know I am a bit late with this, but while adapting the U-Boot >driver >>> >>>> to the new binding I was wondering about the internal PHY >detection: >>> >>>> >>> >>>> >>> >>>> So here you seem to deduce the usage of the internal PHY by the >PHY >>> >>>> interface specified in the DT (MII = internal, RGMII = >external). >>> >>>> I think I raised this question before, but isn't it perfectly >legal for >>> >>>> a board to use MII with an external PHY even on those SoCs that >feature >>> >>>> an internal PHY? >>> >>>> On the first glance that does not make too much sense, but >apart from >>> >>>> not being the correct binding to describe all of the SoCs >features I see >>> >>>> two scenarios: >>> >>>> 1) A board vendor might choose to not use the internal PHY >because it >>> >>>> has bugs, lacks features (configurability) or has other issues. >For >>> >>>> instance I have heard reports that the internal PHY makes the >SoC go >>> >>>> rather hot, possibly limiting the CPU frequency. By using an >external >>> >>>> MII PHY (which are still cheaper than RGMII PHYs) this can be >avoided. >>> >>>> 2) A PHY does not necessarily need to be directly connected to >>> >>>> magnetics. Indeed quite some boards use (RG)MII to connect to a >switch >>> >>>> IC or some other network circuitry, for instance fibre >connectors. >>> >>>> >>> >>>> So I was wondering if we would need an explicit: >>> >>>> allwinner,use-internal-phy; >>> >>>> boolean DT property to signal the usage of the internal PHY? >>> >>>> Alternatively we could go with the negative version: >>> >>>> allwinner,disable-internal-phy; >>> >>>> >>> >>>> Or what about introducing a new "allwinner,internal-mii-phy" >compatible >>> >>>> string for the *PHY* node and use that? >>> >>>> >>> >>>> I just want to avoid that we introduce a binding that causes us >>> >>>> headaches later. I think we can still fix this with a followup >patch >>> >>>> before the driver and its binding hit a release kernel. >>> >>>> >>> >>>> Cheers, >>> >>>> Andre. >>> >>>> >>> >>> >>> >>> I just see some patch, where "phy-mode = internal" is valid. >>> >>> I will try to find a way to use it >>> >> >>> >> Can you provide a link? >>> > >>> > https://lkml.org/lkml/2017/6/23/479 >>> > >>> >> >>> >> I'm not a fan of using phy-mode for this. There's no guarantee >what >>> >> mode the internal PHY uses. That's what phy-mode is for. >>> >>> I can understand Chen-Yu's concerns, but ... >>> >>> > For each soc the internal PHY mode is know and setted in >emac_variant/internal_phy >>> > So its not a problem. >>> >>> that is true as well, at least for now. >>> >>> So while I agree that having a separate property to indicate the >usage >>> of the internal PHY would be nice, I am bit tempted to use this >easier >>> approach and piggy back on the existing phy-mode property. >> >> We're trying to fix an issue that works for now too. >> >> If we want to consider future weird cases, then we must consider all >> of them. And the phy mode changing is definitely not really far >> fetched. > >I guess the issue is whether it's likely that the vendor puts 2 >internal >PHYs in one SoC, and they use different modes and can be switched >around. >Otherwise it's fixed for a given SoC, and we can just handle that with >the per-SoC GMAC compatible. > >Maybe Florian could tell us if this was one of the intended use cases >for the "internal" phy mode. > >As for Rockchip, AFAIK they have 2 MACs, one is connected to the >internal >PHY, while the other is connected to the external interface, and there >is >no muxing involved, unlike Allwinner's solution. > >> I agree with Chen-Yu, and I really feel like the compatible solution >> you suggested would cover both your concerns, and ours. > >If using a PHY compatible is the solution, we could just use the >"ethernet-phy-idAAAA.BBBB" style one, and put in the bogus ID that >Allwinner used. > >Care must be taken to put this at the board level for boards using >the internal PHY, or we'd have to delete or override the property >in all other boards. > >Ideally I think the internal PHY device node should _not_ be in >the SoC level .dtsi file. If we select the external interface, then >there's no connection to the internal PHY, and that device node becomes >unusable and bogus. This is something I think should be fixed >regardless >of the phy-mode discussion above. I think it should be in the SoC DTSI, as it's part of the SoC. But it makes sense to set status to disabled defaultly. > >ChenYu
On Tue, Jun 27, 2017 at 6:17 PM, Icenowy Zheng <icenowy@aosc.io> wrote: > > > 于 2017年6月27日 GMT+08:00 下午6:11:47, Chen-Yu Tsai <wens@csie.org> 写到: >>On Tue, Jun 27, 2017 at 5:41 PM, Maxime Ripard >><maxime.ripard@free-electrons.com> wrote: >>> On Tue, Jun 27, 2017 at 10:02:45AM +0100, Andre Przywara wrote: >>>> Hi, >>>> >>>> (CC:ing some people from that Rockchip dmwac series) >>>> >>>> On 27/06/17 09:21, Corentin Labbe wrote: >>>> > On Tue, Jun 27, 2017 at 04:11:21PM +0800, Chen-Yu Tsai wrote: >>>> >> On Tue, Jun 27, 2017 at 4:05 PM, Corentin Labbe >>>> >> <clabbe.montjoie@gmail.com> wrote: >>>> >>> On Mon, Jun 26, 2017 at 01:18:23AM +0100, André Przywara wrote: >>>> >>>> On 31/05/17 08:18, Corentin Labbe wrote: >>>> >>>>> The dwmac-sun8i is a heavy hacked version of stmmac hardware >>by >>>> >>>>> allwinner. >>>> >>>>> In fact the only common part is the descriptor management and >>the first >>>> >>>>> register function. >>>> >>>> >>>> >>>> Hi, >>>> >>>> >>>> >>>> I know I am a bit late with this, but while adapting the U-Boot >>driver >>>> >>>> to the new binding I was wondering about the internal PHY >>detection: >>>> >>>> >>>> >>>> >>>> >>>> So here you seem to deduce the usage of the internal PHY by the >>PHY >>>> >>>> interface specified in the DT (MII = internal, RGMII = >>external). >>>> >>>> I think I raised this question before, but isn't it perfectly >>legal for >>>> >>>> a board to use MII with an external PHY even on those SoCs that >>feature >>>> >>>> an internal PHY? >>>> >>>> On the first glance that does not make too much sense, but >>apart from >>>> >>>> not being the correct binding to describe all of the SoCs >>features I see >>>> >>>> two scenarios: >>>> >>>> 1) A board vendor might choose to not use the internal PHY >>because it >>>> >>>> has bugs, lacks features (configurability) or has other issues. >>For >>>> >>>> instance I have heard reports that the internal PHY makes the >>SoC go >>>> >>>> rather hot, possibly limiting the CPU frequency. By using an >>external >>>> >>>> MII PHY (which are still cheaper than RGMII PHYs) this can be >>avoided. >>>> >>>> 2) A PHY does not necessarily need to be directly connected to >>>> >>>> magnetics. Indeed quite some boards use (RG)MII to connect to a >>switch >>>> >>>> IC or some other network circuitry, for instance fibre >>connectors. >>>> >>>> >>>> >>>> So I was wondering if we would need an explicit: >>>> >>>> allwinner,use-internal-phy; >>>> >>>> boolean DT property to signal the usage of the internal PHY? >>>> >>>> Alternatively we could go with the negative version: >>>> >>>> allwinner,disable-internal-phy; >>>> >>>> >>>> >>>> Or what about introducing a new "allwinner,internal-mii-phy" >>compatible >>>> >>>> string for the *PHY* node and use that? >>>> >>>> >>>> >>>> I just want to avoid that we introduce a binding that causes us >>>> >>>> headaches later. I think we can still fix this with a followup >>patch >>>> >>>> before the driver and its binding hit a release kernel. >>>> >>>> >>>> >>>> Cheers, >>>> >>>> Andre. >>>> >>>> >>>> >>> >>>> >>> I just see some patch, where "phy-mode = internal" is valid. >>>> >>> I will try to find a way to use it >>>> >> >>>> >> Can you provide a link? >>>> > >>>> > https://lkml.org/lkml/2017/6/23/479 >>>> > >>>> >> >>>> >> I'm not a fan of using phy-mode for this. There's no guarantee >>what >>>> >> mode the internal PHY uses. That's what phy-mode is for. >>>> >>>> I can understand Chen-Yu's concerns, but ... >>>> >>>> > For each soc the internal PHY mode is know and setted in >>emac_variant/internal_phy >>>> > So its not a problem. >>>> >>>> that is true as well, at least for now. >>>> >>>> So while I agree that having a separate property to indicate the >>usage >>>> of the internal PHY would be nice, I am bit tempted to use this >>easier >>>> approach and piggy back on the existing phy-mode property. >>> >>> We're trying to fix an issue that works for now too. >>> >>> If we want to consider future weird cases, then we must consider all >>> of them. And the phy mode changing is definitely not really far >>> fetched. >> >>I guess the issue is whether it's likely that the vendor puts 2 >>internal >>PHYs in one SoC, and they use different modes and can be switched >>around. >>Otherwise it's fixed for a given SoC, and we can just handle that with >>the per-SoC GMAC compatible. >> >>Maybe Florian could tell us if this was one of the intended use cases >>for the "internal" phy mode. >> >>As for Rockchip, AFAIK they have 2 MACs, one is connected to the >>internal >>PHY, while the other is connected to the external interface, and there >>is >>no muxing involved, unlike Allwinner's solution. >> >>> I agree with Chen-Yu, and I really feel like the compatible solution >>> you suggested would cover both your concerns, and ours. >> >>If using a PHY compatible is the solution, we could just use the >>"ethernet-phy-idAAAA.BBBB" style one, and put in the bogus ID that >>Allwinner used. >> >>Care must be taken to put this at the board level for boards using >>the internal PHY, or we'd have to delete or override the property >>in all other boards. >> >>Ideally I think the internal PHY device node should _not_ be in >>the SoC level .dtsi file. If we select the external interface, then >>there's no connection to the internal PHY, and that device node becomes >>unusable and bogus. This is something I think should be fixed >>regardless >>of the phy-mode discussion above. > > I think it should be in the SoC DTSI, as it's part of the SoC. > > But it makes sense to set status to disabled defaultly. Then you end up stepping on it when you add an external PHY with the same address, and start wondering why things don't work. ChenYu
On Tue, Jun 27, 2017 at 6:15 PM, Andre Przywara <andre.przywara@arm.com> wrote: > Hi, > > On 27/06/17 10:41, Maxime Ripard wrote: >> On Tue, Jun 27, 2017 at 10:02:45AM +0100, Andre Przywara wrote: >>> Hi, >>> >>> (CC:ing some people from that Rockchip dmwac series) >>> >>> On 27/06/17 09:21, Corentin Labbe wrote: >>>> On Tue, Jun 27, 2017 at 04:11:21PM +0800, Chen-Yu Tsai wrote: >>>>> On Tue, Jun 27, 2017 at 4:05 PM, Corentin Labbe >>>>> <clabbe.montjoie@gmail.com> wrote: >>>>>> On Mon, Jun 26, 2017 at 01:18:23AM +0100, André Przywara wrote: >>>>>>> On 31/05/17 08:18, Corentin Labbe wrote: >>>>>>>> The dwmac-sun8i is a heavy hacked version of stmmac hardware by >>>>>>>> allwinner. >>>>>>>> In fact the only common part is the descriptor management and the first >>>>>>>> register function. >>>>>>> >>>>>>> Hi, >>>>>>> >>>>>>> I know I am a bit late with this, but while adapting the U-Boot driver >>>>>>> to the new binding I was wondering about the internal PHY detection: >>>>>>> >>>>>>> >>>>>>> So here you seem to deduce the usage of the internal PHY by the PHY >>>>>>> interface specified in the DT (MII = internal, RGMII = external). >>>>>>> I think I raised this question before, but isn't it perfectly legal for >>>>>>> a board to use MII with an external PHY even on those SoCs that feature >>>>>>> an internal PHY? >>>>>>> On the first glance that does not make too much sense, but apart from >>>>>>> not being the correct binding to describe all of the SoCs features I see >>>>>>> two scenarios: >>>>>>> 1) A board vendor might choose to not use the internal PHY because it >>>>>>> has bugs, lacks features (configurability) or has other issues. For >>>>>>> instance I have heard reports that the internal PHY makes the SoC go >>>>>>> rather hot, possibly limiting the CPU frequency. By using an external >>>>>>> MII PHY (which are still cheaper than RGMII PHYs) this can be avoided. >>>>>>> 2) A PHY does not necessarily need to be directly connected to >>>>>>> magnetics. Indeed quite some boards use (RG)MII to connect to a switch >>>>>>> IC or some other network circuitry, for instance fibre connectors. >>>>>>> >>>>>>> So I was wondering if we would need an explicit: >>>>>>> allwinner,use-internal-phy; >>>>>>> boolean DT property to signal the usage of the internal PHY? >>>>>>> Alternatively we could go with the negative version: >>>>>>> allwinner,disable-internal-phy; >>>>>>> >>>>>>> Or what about introducing a new "allwinner,internal-mii-phy" compatible >>>>>>> string for the *PHY* node and use that? >>>>>>> >>>>>>> I just want to avoid that we introduce a binding that causes us >>>>>>> headaches later. I think we can still fix this with a followup patch >>>>>>> before the driver and its binding hit a release kernel. >>>>>>> >>>>>>> Cheers, >>>>>>> Andre. >>>>>>> >>>>>> >>>>>> I just see some patch, where "phy-mode = internal" is valid. >>>>>> I will try to find a way to use it >>>>> >>>>> Can you provide a link? >>>> >>>> https://lkml.org/lkml/2017/6/23/479 >>>> >>>>> >>>>> I'm not a fan of using phy-mode for this. There's no guarantee what >>>>> mode the internal PHY uses. That's what phy-mode is for. >>> >>> I can understand Chen-Yu's concerns, but ... >>> >>>> For each soc the internal PHY mode is know and setted in emac_variant/internal_phy >>>> So its not a problem. >>> >>> that is true as well, at least for now. >>> >>> So while I agree that having a separate property to indicate the usage >>> of the internal PHY would be nice, I am bit tempted to use this easier >>> approach and piggy back on the existing phy-mode property. >> >> We're trying to fix an issue that works for now too. >> >> If we want to consider future weird cases, then we must consider all >> of them. And the phy mode changing is definitely not really far >> fetched. >> >> I agree with Chen-Yu, and I really feel like the compatible solution >> you suggested would cover both your concerns, and ours. > > So something like this? > emac: emac@1c30000 { > compatible = "allwinner,sun8i-h3-emac"; > ... > phy-mode = "mii"; > phy-handle = <&int_mii_phy>; > ... > > mdio: mdio { > #address-cells = <1>; > #size-cells = <0>; > int_mii_phy: ethernet-phy@1 { > compatible = "allwinner,sun8i-h3-ephy"; > syscon = <&syscon>; > reg = <1>; > clocks = <&ccu CLK_BUS_EPHY>; > resets = <&ccu RST_BUS_EPHY>; > }; > }; > }; > > And then move the internal-PHY setup code into a separate PHY driver? > > That looks like the architecturally best solution to me, but is probably > also a bit involved since it would require a separate PHY driver. > Or can we make it simpler, but still use this binding? This was my initial approach prior to handing it off to Corentin. The MDIO bus is discoverable, so in the kernel MDIO bus driver code, the devices are only created if something responds. However, for the EPHY to respond, you must first configure the clocks, reset controls, and syscon registers. You need either a platform device driver for that, or do it in the MAC driver. The latter made more sense at the time, looking at how the device tree is structured. ChenYu
于 2017年6月27日 GMT+08:00 下午6:15:58, Andre Przywara <andre.przywara@arm.com> 写到: >Hi, > >On 27/06/17 10:41, Maxime Ripard wrote: >> On Tue, Jun 27, 2017 at 10:02:45AM +0100, Andre Przywara wrote: >>> Hi, >>> >>> (CC:ing some people from that Rockchip dmwac series) >>> >>> On 27/06/17 09:21, Corentin Labbe wrote: >>>> On Tue, Jun 27, 2017 at 04:11:21PM +0800, Chen-Yu Tsai wrote: >>>>> On Tue, Jun 27, 2017 at 4:05 PM, Corentin Labbe >>>>> <clabbe.montjoie@gmail.com> wrote: >>>>>> On Mon, Jun 26, 2017 at 01:18:23AM +0100, André Przywara wrote: >>>>>>> On 31/05/17 08:18, Corentin Labbe wrote: >>>>>>>> The dwmac-sun8i is a heavy hacked version of stmmac hardware by >>>>>>>> allwinner. >>>>>>>> In fact the only common part is the descriptor management and >the first >>>>>>>> register function. >>>>>>> >>>>>>> Hi, >>>>>>> >>>>>>> I know I am a bit late with this, but while adapting the U-Boot >driver >>>>>>> to the new binding I was wondering about the internal PHY >detection: >>>>>>> >>>>>>> >>>>>>> So here you seem to deduce the usage of the internal PHY by the >PHY >>>>>>> interface specified in the DT (MII = internal, RGMII = >external). >>>>>>> I think I raised this question before, but isn't it perfectly >legal for >>>>>>> a board to use MII with an external PHY even on those SoCs that >feature >>>>>>> an internal PHY? >>>>>>> On the first glance that does not make too much sense, but apart >from >>>>>>> not being the correct binding to describe all of the SoCs >features I see >>>>>>> two scenarios: >>>>>>> 1) A board vendor might choose to not use the internal PHY >because it >>>>>>> has bugs, lacks features (configurability) or has other issues. >For >>>>>>> instance I have heard reports that the internal PHY makes the >SoC go >>>>>>> rather hot, possibly limiting the CPU frequency. By using an >external >>>>>>> MII PHY (which are still cheaper than RGMII PHYs) this can be >avoided. >>>>>>> 2) A PHY does not necessarily need to be directly connected to >>>>>>> magnetics. Indeed quite some boards use (RG)MII to connect to a >switch >>>>>>> IC or some other network circuitry, for instance fibre >connectors. >>>>>>> >>>>>>> So I was wondering if we would need an explicit: >>>>>>> allwinner,use-internal-phy; >>>>>>> boolean DT property to signal the usage of the internal PHY? >>>>>>> Alternatively we could go with the negative version: >>>>>>> allwinner,disable-internal-phy; >>>>>>> >>>>>>> Or what about introducing a new "allwinner,internal-mii-phy" >compatible >>>>>>> string for the *PHY* node and use that? >>>>>>> >>>>>>> I just want to avoid that we introduce a binding that causes us >>>>>>> headaches later. I think we can still fix this with a followup >patch >>>>>>> before the driver and its binding hit a release kernel. >>>>>>> >>>>>>> Cheers, >>>>>>> Andre. >>>>>>> >>>>>> >>>>>> I just see some patch, where "phy-mode = internal" is valid. >>>>>> I will try to find a way to use it >>>>> >>>>> Can you provide a link? >>>> >>>> https://lkml.org/lkml/2017/6/23/479 >>>> >>>>> >>>>> I'm not a fan of using phy-mode for this. There's no guarantee >what >>>>> mode the internal PHY uses. That's what phy-mode is for. >>> >>> I can understand Chen-Yu's concerns, but ... >>> >>>> For each soc the internal PHY mode is know and setted in >emac_variant/internal_phy >>>> So its not a problem. >>> >>> that is true as well, at least for now. >>> >>> So while I agree that having a separate property to indicate the >usage >>> of the internal PHY would be nice, I am bit tempted to use this >easier >>> approach and piggy back on the existing phy-mode property. >> >> We're trying to fix an issue that works for now too. >> >> If we want to consider future weird cases, then we must consider all >> of them. And the phy mode changing is definitely not really far >> fetched. >> >> I agree with Chen-Yu, and I really feel like the compatible solution >> you suggested would cover both your concerns, and ours. > >So something like this? > emac: emac@1c30000 { > compatible = "allwinner,sun8i-h3-emac"; > ... > phy-mode = "mii"; > phy-handle = <&int_mii_phy>; > ... > > mdio: mdio { > #address-cells = <1>; > #size-cells = <0>; > int_mii_phy: ethernet-phy@1 { > compatible = "allwinner,sun8i-h3-ephy"; > syscon = <&syscon>; The MAC still needs to set some bits of syscon register. > reg = <1>; > clocks = <&ccu CLK_BUS_EPHY>; > resets = <&ccu RST_BUS_EPHY>; > }; > }; > }; > >And then move the internal-PHY setup code into a separate PHY driver? > >That looks like the architecturally best solution to me, but is >probably >also a bit involved since it would require a separate PHY driver. >Or can we make it simpler, but still use this binding? > >Cheers, >Andre.
Hi, On 27/06/17 11:23, Icenowy Zheng wrote: > > > 于 2017年6月27日 GMT+08:00 下午6:15:58, Andre Przywara <andre.przywara@arm.com> 写到: >> Hi, >> >> On 27/06/17 10:41, Maxime Ripard wrote: >>> On Tue, Jun 27, 2017 at 10:02:45AM +0100, Andre Przywara wrote: >>>> Hi, >>>> >>>> (CC:ing some people from that Rockchip dmwac series) >>>> >>>> On 27/06/17 09:21, Corentin Labbe wrote: >>>>> On Tue, Jun 27, 2017 at 04:11:21PM +0800, Chen-Yu Tsai wrote: >>>>>> On Tue, Jun 27, 2017 at 4:05 PM, Corentin Labbe >>>>>> <clabbe.montjoie@gmail.com> wrote: >>>>>>> On Mon, Jun 26, 2017 at 01:18:23AM +0100, André Przywara wrote: >>>>>>>> On 31/05/17 08:18, Corentin Labbe wrote: >>>>>>>>> The dwmac-sun8i is a heavy hacked version of stmmac hardware by >>>>>>>>> allwinner. >>>>>>>>> In fact the only common part is the descriptor management and >> the first >>>>>>>>> register function. >>>>>>>> >>>>>>>> Hi, >>>>>>>> >>>>>>>> I know I am a bit late with this, but while adapting the U-Boot >> driver >>>>>>>> to the new binding I was wondering about the internal PHY >> detection: >>>>>>>> >>>>>>>> >>>>>>>> So here you seem to deduce the usage of the internal PHY by the >> PHY >>>>>>>> interface specified in the DT (MII = internal, RGMII = >> external). >>>>>>>> I think I raised this question before, but isn't it perfectly >> legal for >>>>>>>> a board to use MII with an external PHY even on those SoCs that >> feature >>>>>>>> an internal PHY? >>>>>>>> On the first glance that does not make too much sense, but apart >> from >>>>>>>> not being the correct binding to describe all of the SoCs >> features I see >>>>>>>> two scenarios: >>>>>>>> 1) A board vendor might choose to not use the internal PHY >> because it >>>>>>>> has bugs, lacks features (configurability) or has other issues. >> For >>>>>>>> instance I have heard reports that the internal PHY makes the >> SoC go >>>>>>>> rather hot, possibly limiting the CPU frequency. By using an >> external >>>>>>>> MII PHY (which are still cheaper than RGMII PHYs) this can be >> avoided. >>>>>>>> 2) A PHY does not necessarily need to be directly connected to >>>>>>>> magnetics. Indeed quite some boards use (RG)MII to connect to a >> switch >>>>>>>> IC or some other network circuitry, for instance fibre >> connectors. >>>>>>>> >>>>>>>> So I was wondering if we would need an explicit: >>>>>>>> allwinner,use-internal-phy; >>>>>>>> boolean DT property to signal the usage of the internal PHY? >>>>>>>> Alternatively we could go with the negative version: >>>>>>>> allwinner,disable-internal-phy; >>>>>>>> >>>>>>>> Or what about introducing a new "allwinner,internal-mii-phy" >> compatible >>>>>>>> string for the *PHY* node and use that? >>>>>>>> >>>>>>>> I just want to avoid that we introduce a binding that causes us >>>>>>>> headaches later. I think we can still fix this with a followup >> patch >>>>>>>> before the driver and its binding hit a release kernel. >>>>>>>> >>>>>>>> Cheers, >>>>>>>> Andre. >>>>>>>> >>>>>>> >>>>>>> I just see some patch, where "phy-mode = internal" is valid. >>>>>>> I will try to find a way to use it >>>>>> >>>>>> Can you provide a link? >>>>> >>>>> https://lkml.org/lkml/2017/6/23/479 >>>>> >>>>>> >>>>>> I'm not a fan of using phy-mode for this. There's no guarantee >> what >>>>>> mode the internal PHY uses. That's what phy-mode is for. >>>> >>>> I can understand Chen-Yu's concerns, but ... >>>> >>>>> For each soc the internal PHY mode is know and setted in >> emac_variant/internal_phy >>>>> So its not a problem. >>>> >>>> that is true as well, at least for now. >>>> >>>> So while I agree that having a separate property to indicate the >> usage >>>> of the internal PHY would be nice, I am bit tempted to use this >> easier >>>> approach and piggy back on the existing phy-mode property. >>> >>> We're trying to fix an issue that works for now too. >>> >>> If we want to consider future weird cases, then we must consider all >>> of them. And the phy mode changing is definitely not really far >>> fetched. >>> >>> I agree with Chen-Yu, and I really feel like the compatible solution >>> you suggested would cover both your concerns, and ours. >> >> So something like this? >> emac: emac@1c30000 { >> compatible = "allwinner,sun8i-h3-emac"; >> ... >> phy-mode = "mii"; >> phy-handle = <&int_mii_phy>; >> ... >> >> mdio: mdio { >> #address-cells = <1>; >> #size-cells = <0>; >> int_mii_phy: ethernet-phy@1 { >> compatible = "allwinner,sun8i-h3-ephy"; >> syscon = <&syscon>; > > The MAC still needs to set some bits of syscon register. Yes, the syscon property needs also to be in the MAC node, that was meant to be somewhere in the second "..." ;-) But now since Chen-Yu mentioned that we need to set up the PHY *first* to make it actually discoverable via MDIO, I wonder if we could change this to: 1) have the DT as described here 2) Let the dwmac-sun8i driver peek into the node referenced by phy-handle and check the compatible string there. 3) If that matches some allwinner internal PHY name, it sets up the PHY to make it respond when the MDIO driver queries its bus. Or can a PHY driver set itself up (since we have clocks and resets properties in there) *before* the MDIO bus gets scanned? Chen-Yu's comment in the other mail hints at that this is not easily possible. Cheers, Andre. > >> reg = <1>; >> clocks = <&ccu CLK_BUS_EPHY>; >> resets = <&ccu RST_BUS_EPHY>; >> }; >> }; >> }; >> >> And then move the internal-PHY setup code into a separate PHY driver? >> >> That looks like the architecturally best solution to me, but is >> probably >> also a bit involved since it would require a separate PHY driver. >> Or can we make it simpler, but still use this binding? >> >> Cheers, >> Andre.
On Tue, Jun 27, 2017 at 11:33:56AM +0100, Andre Przywara wrote: > Hi, > > On 27/06/17 11:23, Icenowy Zheng wrote: > > > > > > 于 2017年6月27日 GMT+08:00 下午6:15:58, Andre Przywara <andre.przywara@arm.com> 写到: > >> Hi, > >> > >> On 27/06/17 10:41, Maxime Ripard wrote: > >>> On Tue, Jun 27, 2017 at 10:02:45AM +0100, Andre Przywara wrote: > >>>> Hi, > >>>> > >>>> (CC:ing some people from that Rockchip dmwac series) > >>>> > >>>> On 27/06/17 09:21, Corentin Labbe wrote: > >>>>> On Tue, Jun 27, 2017 at 04:11:21PM +0800, Chen-Yu Tsai wrote: > >>>>>> On Tue, Jun 27, 2017 at 4:05 PM, Corentin Labbe > >>>>>> <clabbe.montjoie@gmail.com> wrote: > >>>>>>> On Mon, Jun 26, 2017 at 01:18:23AM +0100, André Przywara wrote: > >>>>>>>> On 31/05/17 08:18, Corentin Labbe wrote: > >>>>>>>>> The dwmac-sun8i is a heavy hacked version of stmmac hardware by > >>>>>>>>> allwinner. > >>>>>>>>> In fact the only common part is the descriptor management and > >> the first > >>>>>>>>> register function. > >>>>>>>> > >>>>>>>> Hi, > >>>>>>>> > >>>>>>>> I know I am a bit late with this, but while adapting the U-Boot > >> driver > >>>>>>>> to the new binding I was wondering about the internal PHY > >> detection: > >>>>>>>> > >>>>>>>> > >>>>>>>> So here you seem to deduce the usage of the internal PHY by the > >> PHY > >>>>>>>> interface specified in the DT (MII = internal, RGMII = > >> external). > >>>>>>>> I think I raised this question before, but isn't it perfectly > >> legal for > >>>>>>>> a board to use MII with an external PHY even on those SoCs that > >> feature > >>>>>>>> an internal PHY? > >>>>>>>> On the first glance that does not make too much sense, but apart > >> from > >>>>>>>> not being the correct binding to describe all of the SoCs > >> features I see > >>>>>>>> two scenarios: > >>>>>>>> 1) A board vendor might choose to not use the internal PHY > >> because it > >>>>>>>> has bugs, lacks features (configurability) or has other issues. > >> For > >>>>>>>> instance I have heard reports that the internal PHY makes the > >> SoC go > >>>>>>>> rather hot, possibly limiting the CPU frequency. By using an > >> external > >>>>>>>> MII PHY (which are still cheaper than RGMII PHYs) this can be > >> avoided. > >>>>>>>> 2) A PHY does not necessarily need to be directly connected to > >>>>>>>> magnetics. Indeed quite some boards use (RG)MII to connect to a > >> switch > >>>>>>>> IC or some other network circuitry, for instance fibre > >> connectors. > >>>>>>>> > >>>>>>>> So I was wondering if we would need an explicit: > >>>>>>>> allwinner,use-internal-phy; > >>>>>>>> boolean DT property to signal the usage of the internal PHY? > >>>>>>>> Alternatively we could go with the negative version: > >>>>>>>> allwinner,disable-internal-phy; > >>>>>>>> > >>>>>>>> Or what about introducing a new "allwinner,internal-mii-phy" > >> compatible > >>>>>>>> string for the *PHY* node and use that? > >>>>>>>> > >>>>>>>> I just want to avoid that we introduce a binding that causes us > >>>>>>>> headaches later. I think we can still fix this with a followup > >> patch > >>>>>>>> before the driver and its binding hit a release kernel. > >>>>>>>> > >>>>>>>> Cheers, > >>>>>>>> Andre. > >>>>>>>> > >>>>>>> > >>>>>>> I just see some patch, where "phy-mode = internal" is valid. > >>>>>>> I will try to find a way to use it > >>>>>> > >>>>>> Can you provide a link? > >>>>> > >>>>> https://lkml.org/lkml/2017/6/23/479 > >>>>> > >>>>>> > >>>>>> I'm not a fan of using phy-mode for this. There's no guarantee > >> what > >>>>>> mode the internal PHY uses. That's what phy-mode is for. > >>>> > >>>> I can understand Chen-Yu's concerns, but ... > >>>> > >>>>> For each soc the internal PHY mode is know and setted in > >> emac_variant/internal_phy > >>>>> So its not a problem. > >>>> > >>>> that is true as well, at least for now. > >>>> > >>>> So while I agree that having a separate property to indicate the > >> usage > >>>> of the internal PHY would be nice, I am bit tempted to use this > >> easier > >>>> approach and piggy back on the existing phy-mode property. > >>> > >>> We're trying to fix an issue that works for now too. > >>> > >>> If we want to consider future weird cases, then we must consider all > >>> of them. And the phy mode changing is definitely not really far > >>> fetched. > >>> > >>> I agree with Chen-Yu, and I really feel like the compatible solution > >>> you suggested would cover both your concerns, and ours. > >> > >> So something like this? > >> emac: emac@1c30000 { > >> compatible = "allwinner,sun8i-h3-emac"; > >> ... > >> phy-mode = "mii"; > >> phy-handle = <&int_mii_phy>; > >> ... > >> > >> mdio: mdio { > >> #address-cells = <1>; > >> #size-cells = <0>; > >> int_mii_phy: ethernet-phy@1 { > >> compatible = "allwinner,sun8i-h3-ephy"; > >> syscon = <&syscon>; > > > > The MAC still needs to set some bits of syscon register. > > Yes, the syscon property needs also to be in the MAC node, that was > meant to be somewhere in the second "..." ;-) > > But now since Chen-Yu mentioned that we need to set up the PHY *first* > to make it actually discoverable via MDIO, I wonder if we could change > this to: > 1) have the DT as described here > 2) Let the dwmac-sun8i driver peek into the node referenced by > phy-handle and check the compatible string there. > 3) If that matches some allwinner internal PHY name, it sets up the PHY > to make it respond when the MDIO driver queries its bus. > > Or can a PHY driver set itself up (since we have clocks and resets > properties in there) *before* the MDIO bus gets scanned? > Chen-Yu's comment in the other mail hints at that this is not easily > possible. > > Cheers, > Andre. > I think adding phy compatible just make things more complex. I think the patch series I sent early fix all problems without more complexity since: - it does not add more DT stuff - it use an already used in tree DT phy-mode "internal" (and so phy mode PHY_INTERFACE_MODE_INTERNAL) Regards
On Tue, Jun 27, 2017 at 11:33:56AM +0100, Andre Przywara wrote: > Hi, > > On 27/06/17 11:23, Icenowy Zheng wrote: > > > > > > 于 2017年6月27日 GMT+08:00 下午6:15:58, Andre Przywara <andre.przywara@arm.com> 写到: > >> Hi, > >> > >> On 27/06/17 10:41, Maxime Ripard wrote: > >>> On Tue, Jun 27, 2017 at 10:02:45AM +0100, Andre Przywara wrote: > >>>> Hi, > >>>> > >>>> (CC:ing some people from that Rockchip dmwac series) > >>>> > >>>> On 27/06/17 09:21, Corentin Labbe wrote: > >>>>> On Tue, Jun 27, 2017 at 04:11:21PM +0800, Chen-Yu Tsai wrote: > >>>>>> On Tue, Jun 27, 2017 at 4:05 PM, Corentin Labbe > >>>>>> <clabbe.montjoie@gmail.com> wrote: > >>>>>>> On Mon, Jun 26, 2017 at 01:18:23AM +0100, André Przywara wrote: > >>>>>>>> On 31/05/17 08:18, Corentin Labbe wrote: > >>>>>>>>> The dwmac-sun8i is a heavy hacked version of stmmac hardware by > >>>>>>>>> allwinner. > >>>>>>>>> In fact the only common part is the descriptor management and > >> the first > >>>>>>>>> register function. > >>>>>>>> > >>>>>>>> Hi, > >>>>>>>> > >>>>>>>> I know I am a bit late with this, but while adapting the U-Boot > >> driver > >>>>>>>> to the new binding I was wondering about the internal PHY > >> detection: > >>>>>>>> > >>>>>>>> > >>>>>>>> So here you seem to deduce the usage of the internal PHY by the > >> PHY > >>>>>>>> interface specified in the DT (MII = internal, RGMII = > >> external). > >>>>>>>> I think I raised this question before, but isn't it perfectly > >> legal for > >>>>>>>> a board to use MII with an external PHY even on those SoCs that > >> feature > >>>>>>>> an internal PHY? > >>>>>>>> On the first glance that does not make too much sense, but apart > >> from > >>>>>>>> not being the correct binding to describe all of the SoCs > >> features I see > >>>>>>>> two scenarios: > >>>>>>>> 1) A board vendor might choose to not use the internal PHY > >> because it > >>>>>>>> has bugs, lacks features (configurability) or has other issues. > >> For > >>>>>>>> instance I have heard reports that the internal PHY makes the > >> SoC go > >>>>>>>> rather hot, possibly limiting the CPU frequency. By using an > >> external > >>>>>>>> MII PHY (which are still cheaper than RGMII PHYs) this can be > >> avoided. > >>>>>>>> 2) A PHY does not necessarily need to be directly connected to > >>>>>>>> magnetics. Indeed quite some boards use (RG)MII to connect to a > >> switch > >>>>>>>> IC or some other network circuitry, for instance fibre > >> connectors. > >>>>>>>> > >>>>>>>> So I was wondering if we would need an explicit: > >>>>>>>> allwinner,use-internal-phy; > >>>>>>>> boolean DT property to signal the usage of the internal PHY? > >>>>>>>> Alternatively we could go with the negative version: > >>>>>>>> allwinner,disable-internal-phy; > >>>>>>>> > >>>>>>>> Or what about introducing a new "allwinner,internal-mii-phy" > >> compatible > >>>>>>>> string for the *PHY* node and use that? > >>>>>>>> > >>>>>>>> I just want to avoid that we introduce a binding that causes us > >>>>>>>> headaches later. I think we can still fix this with a followup > >> patch > >>>>>>>> before the driver and its binding hit a release kernel. > >>>>>>>> > >>>>>>>> Cheers, > >>>>>>>> Andre. > >>>>>>>> > >>>>>>> > >>>>>>> I just see some patch, where "phy-mode = internal" is valid. > >>>>>>> I will try to find a way to use it > >>>>>> > >>>>>> Can you provide a link? > >>>>> > >>>>> https://lkml.org/lkml/2017/6/23/479 > >>>>> > >>>>>> > >>>>>> I'm not a fan of using phy-mode for this. There's no guarantee > >> what > >>>>>> mode the internal PHY uses. That's what phy-mode is for. > >>>> > >>>> I can understand Chen-Yu's concerns, but ... > >>>> > >>>>> For each soc the internal PHY mode is know and setted in > >> emac_variant/internal_phy > >>>>> So its not a problem. > >>>> > >>>> that is true as well, at least for now. > >>>> > >>>> So while I agree that having a separate property to indicate the > >> usage > >>>> of the internal PHY would be nice, I am bit tempted to use this > >> easier > >>>> approach and piggy back on the existing phy-mode property. > >>> > >>> We're trying to fix an issue that works for now too. > >>> > >>> If we want to consider future weird cases, then we must consider all > >>> of them. And the phy mode changing is definitely not really far > >>> fetched. > >>> > >>> I agree with Chen-Yu, and I really feel like the compatible solution > >>> you suggested would cover both your concerns, and ours. > >> > >> So something like this? > >> emac: emac@1c30000 { > >> compatible = "allwinner,sun8i-h3-emac"; > >> ... > >> phy-mode = "mii"; > >> phy-handle = <&int_mii_phy>; > >> ... > >> > >> mdio: mdio { > >> #address-cells = <1>; > >> #size-cells = <0>; > >> int_mii_phy: ethernet-phy@1 { > >> compatible = "allwinner,sun8i-h3-ephy"; > >> syscon = <&syscon>; > > > > The MAC still needs to set some bits of syscon register. > > Yes, the syscon property needs also to be in the MAC node, that was > meant to be somewhere in the second "..." ;-) > > But now since Chen-Yu mentioned that we need to set up the PHY *first* > to make it actually discoverable via MDIO, I wonder if we could change > this to: > 1) have the DT as described here > 2) Let the dwmac-sun8i driver peek into the node referenced by > phy-handle and check the compatible string there. > 3) If that matches some allwinner internal PHY name, it sets up the PHY > to make it respond when the MDIO driver queries its bus. That would be quite easy to do, and would be my implementation of choice yes. > Or can a PHY driver set itself up (since we have clocks and resets > properties in there) *before* the MDIO bus gets scanned? > Chen-Yu's comment in the other mail hints at that this is not easily > possible. Yeah, that's not easily doable, it would require your driver to probe before your device has showed up, which is not quite what the driver model is made like. Maxime
On Tue, Jun 27, 2017 at 02:37:48PM +0200, Corentin Labbe wrote: > On Tue, Jun 27, 2017 at 11:33:56AM +0100, Andre Przywara wrote: > > Hi, > > > > On 27/06/17 11:23, Icenowy Zheng wrote: > > > > > > > > > 于 2017年6月27日 GMT+08:00 下午6:15:58, Andre Przywara <andre.przywara@arm.com> 写到: > > >> Hi, > > >> > > >> On 27/06/17 10:41, Maxime Ripard wrote: > > >>> On Tue, Jun 27, 2017 at 10:02:45AM +0100, Andre Przywara wrote: > > >>>> Hi, > > >>>> > > >>>> (CC:ing some people from that Rockchip dmwac series) > > >>>> > > >>>> On 27/06/17 09:21, Corentin Labbe wrote: > > >>>>> On Tue, Jun 27, 2017 at 04:11:21PM +0800, Chen-Yu Tsai wrote: > > >>>>>> On Tue, Jun 27, 2017 at 4:05 PM, Corentin Labbe > > >>>>>> <clabbe.montjoie@gmail.com> wrote: > > >>>>>>> On Mon, Jun 26, 2017 at 01:18:23AM +0100, André Przywara wrote: > > >>>>>>>> On 31/05/17 08:18, Corentin Labbe wrote: > > >>>>>>>>> The dwmac-sun8i is a heavy hacked version of stmmac hardware by > > >>>>>>>>> allwinner. > > >>>>>>>>> In fact the only common part is the descriptor management and > > >> the first > > >>>>>>>>> register function. > > >>>>>>>> > > >>>>>>>> Hi, > > >>>>>>>> > > >>>>>>>> I know I am a bit late with this, but while adapting the U-Boot > > >> driver > > >>>>>>>> to the new binding I was wondering about the internal PHY > > >> detection: > > >>>>>>>> > > >>>>>>>> > > >>>>>>>> So here you seem to deduce the usage of the internal PHY by the > > >> PHY > > >>>>>>>> interface specified in the DT (MII = internal, RGMII = > > >> external). > > >>>>>>>> I think I raised this question before, but isn't it perfectly > > >> legal for > > >>>>>>>> a board to use MII with an external PHY even on those SoCs that > > >> feature > > >>>>>>>> an internal PHY? > > >>>>>>>> On the first glance that does not make too much sense, but apart > > >> from > > >>>>>>>> not being the correct binding to describe all of the SoCs > > >> features I see > > >>>>>>>> two scenarios: > > >>>>>>>> 1) A board vendor might choose to not use the internal PHY > > >> because it > > >>>>>>>> has bugs, lacks features (configurability) or has other issues. > > >> For > > >>>>>>>> instance I have heard reports that the internal PHY makes the > > >> SoC go > > >>>>>>>> rather hot, possibly limiting the CPU frequency. By using an > > >> external > > >>>>>>>> MII PHY (which are still cheaper than RGMII PHYs) this can be > > >> avoided. > > >>>>>>>> 2) A PHY does not necessarily need to be directly connected to > > >>>>>>>> magnetics. Indeed quite some boards use (RG)MII to connect to a > > >> switch > > >>>>>>>> IC or some other network circuitry, for instance fibre > > >> connectors. > > >>>>>>>> > > >>>>>>>> So I was wondering if we would need an explicit: > > >>>>>>>> allwinner,use-internal-phy; > > >>>>>>>> boolean DT property to signal the usage of the internal PHY? > > >>>>>>>> Alternatively we could go with the negative version: > > >>>>>>>> allwinner,disable-internal-phy; > > >>>>>>>> > > >>>>>>>> Or what about introducing a new "allwinner,internal-mii-phy" > > >> compatible > > >>>>>>>> string for the *PHY* node and use that? > > >>>>>>>> > > >>>>>>>> I just want to avoid that we introduce a binding that causes us > > >>>>>>>> headaches later. I think we can still fix this with a followup > > >> patch > > >>>>>>>> before the driver and its binding hit a release kernel. > > >>>>>>>> > > >>>>>>>> Cheers, > > >>>>>>>> Andre. > > >>>>>>>> > > >>>>>>> > > >>>>>>> I just see some patch, where "phy-mode = internal" is valid. > > >>>>>>> I will try to find a way to use it > > >>>>>> > > >>>>>> Can you provide a link? > > >>>>> > > >>>>> https://lkml.org/lkml/2017/6/23/479 > > >>>>> > > >>>>>> > > >>>>>> I'm not a fan of using phy-mode for this. There's no guarantee > > >> what > > >>>>>> mode the internal PHY uses. That's what phy-mode is for. > > >>>> > > >>>> I can understand Chen-Yu's concerns, but ... > > >>>> > > >>>>> For each soc the internal PHY mode is know and setted in > > >> emac_variant/internal_phy > > >>>>> So its not a problem. > > >>>> > > >>>> that is true as well, at least for now. > > >>>> > > >>>> So while I agree that having a separate property to indicate > > >>>> the usage of the internal PHY would be nice, I am bit tempted > > >>>> to use this easier approach and piggy back on the existing > > >>>> phy-mode property. > > >>> > > >>> We're trying to fix an issue that works for now too. > > >>> > > >>> If we want to consider future weird cases, then we must > > >>> consider all of them. And the phy mode changing is definitely > > >>> not really far fetched. > > >>> > > >>> I agree with Chen-Yu, and I really feel like the compatible > > >>> solution you suggested would cover both your concerns, and > > >>> ours. > > >> > > >> So something like this? > > >> emac: emac@1c30000 { > > >> compatible = "allwinner,sun8i-h3-emac"; > > >> ... > > >> phy-mode = "mii"; > > >> phy-handle = <&int_mii_phy>; > > >> ... > > >> > > >> mdio: mdio { > > >> #address-cells = <1>; > > >> #size-cells = <0>; > > >> int_mii_phy: ethernet-phy@1 { > > >> compatible = "allwinner,sun8i-h3-ephy"; > > >> syscon = <&syscon>; > > > > > > The MAC still needs to set some bits of syscon register. > > > > Yes, the syscon property needs also to be in the MAC node, that > > was meant to be somewhere in the second "..." ;-) > > > > But now since Chen-Yu mentioned that we need to set up the PHY *first* > > to make it actually discoverable via MDIO, I wonder if we could change > > this to: > > 1) have the DT as described here > > 2) Let the dwmac-sun8i driver peek into the node referenced by > > phy-handle and check the compatible string there. > > 3) If that matches some allwinner internal PHY name, it sets up the PHY > > to make it respond when the MDIO driver queries its bus. > > > > Or can a PHY driver set itself up (since we have clocks and resets > > properties in there) *before* the MDIO bus gets scanned? > > Chen-Yu's comment in the other mail hints at that this is not easily > > possible. > > I think adding phy compatible just make things more complex. > > I think the patch series I sent early fix all problems without more > complexity since: > > - it does not add more DT stuff > - it use an already used in tree DT phy-mode "internal" (and so phy > mode PHY_INTERFACE_MODE_INTERNAL) - it doesn't cover all the concerns we had - it uses an undocumented value, with an unclear implication Maxime
On Tue, Jun 27, 2017 at 07:29:37PM +0200, Maxime Ripard wrote: > On Tue, Jun 27, 2017 at 02:37:48PM +0200, Corentin Labbe wrote: > > On Tue, Jun 27, 2017 at 11:33:56AM +0100, Andre Przywara wrote: > > > Hi, > > > > > > On 27/06/17 11:23, Icenowy Zheng wrote: > > > > > > > > > > > > 于 2017年6月27日 GMT+08:00 下午6:15:58, Andre Przywara <andre.przywara@arm.com> 写到: > > > >> Hi, > > > >> > > > >> On 27/06/17 10:41, Maxime Ripard wrote: > > > >>> On Tue, Jun 27, 2017 at 10:02:45AM +0100, Andre Przywara wrote: > > > >>>> Hi, > > > >>>> > > > >>>> (CC:ing some people from that Rockchip dmwac series) > > > >>>> > > > >>>> On 27/06/17 09:21, Corentin Labbe wrote: > > > >>>>> On Tue, Jun 27, 2017 at 04:11:21PM +0800, Chen-Yu Tsai wrote: > > > >>>>>> On Tue, Jun 27, 2017 at 4:05 PM, Corentin Labbe > > > >>>>>> <clabbe.montjoie@gmail.com> wrote: > > > >>>>>>> On Mon, Jun 26, 2017 at 01:18:23AM +0100, André Przywara wrote: > > > >>>>>>>> On 31/05/17 08:18, Corentin Labbe wrote: > > > >>>>>>>>> The dwmac-sun8i is a heavy hacked version of stmmac hardware by > > > >>>>>>>>> allwinner. > > > >>>>>>>>> In fact the only common part is the descriptor management and > > > >> the first > > > >>>>>>>>> register function. > > > >>>>>>>> > > > >>>>>>>> Hi, > > > >>>>>>>> > > > >>>>>>>> I know I am a bit late with this, but while adapting the U-Boot > > > >> driver > > > >>>>>>>> to the new binding I was wondering about the internal PHY > > > >> detection: > > > >>>>>>>> > > > >>>>>>>> > > > >>>>>>>> So here you seem to deduce the usage of the internal PHY by the > > > >> PHY > > > >>>>>>>> interface specified in the DT (MII = internal, RGMII = > > > >> external). > > > >>>>>>>> I think I raised this question before, but isn't it perfectly > > > >> legal for > > > >>>>>>>> a board to use MII with an external PHY even on those SoCs that > > > >> feature > > > >>>>>>>> an internal PHY? > > > >>>>>>>> On the first glance that does not make too much sense, but apart > > > >> from > > > >>>>>>>> not being the correct binding to describe all of the SoCs > > > >> features I see > > > >>>>>>>> two scenarios: > > > >>>>>>>> 1) A board vendor might choose to not use the internal PHY > > > >> because it > > > >>>>>>>> has bugs, lacks features (configurability) or has other issues. > > > >> For > > > >>>>>>>> instance I have heard reports that the internal PHY makes the > > > >> SoC go > > > >>>>>>>> rather hot, possibly limiting the CPU frequency. By using an > > > >> external > > > >>>>>>>> MII PHY (which are still cheaper than RGMII PHYs) this can be > > > >> avoided. > > > >>>>>>>> 2) A PHY does not necessarily need to be directly connected to > > > >>>>>>>> magnetics. Indeed quite some boards use (RG)MII to connect to a > > > >> switch > > > >>>>>>>> IC or some other network circuitry, for instance fibre > > > >> connectors. > > > >>>>>>>> > > > >>>>>>>> So I was wondering if we would need an explicit: > > > >>>>>>>> allwinner,use-internal-phy; > > > >>>>>>>> boolean DT property to signal the usage of the internal PHY? > > > >>>>>>>> Alternatively we could go with the negative version: > > > >>>>>>>> allwinner,disable-internal-phy; > > > >>>>>>>> > > > >>>>>>>> Or what about introducing a new "allwinner,internal-mii-phy" > > > >> compatible > > > >>>>>>>> string for the *PHY* node and use that? > > > >>>>>>>> > > > >>>>>>>> I just want to avoid that we introduce a binding that causes us > > > >>>>>>>> headaches later. I think we can still fix this with a followup > > > >> patch > > > >>>>>>>> before the driver and its binding hit a release kernel. > > > >>>>>>>> > > > >>>>>>>> Cheers, > > > >>>>>>>> Andre. > > > >>>>>>>> > > > >>>>>>> > > > >>>>>>> I just see some patch, where "phy-mode = internal" is valid. > > > >>>>>>> I will try to find a way to use it > > > >>>>>> > > > >>>>>> Can you provide a link? > > > >>>>> > > > >>>>> https://lkml.org/lkml/2017/6/23/479 > > > >>>>> > > > >>>>>> > > > >>>>>> I'm not a fan of using phy-mode for this. There's no guarantee > > > >> what > > > >>>>>> mode the internal PHY uses. That's what phy-mode is for. > > > >>>> > > > >>>> I can understand Chen-Yu's concerns, but ... > > > >>>> > > > >>>>> For each soc the internal PHY mode is know and setted in > > > >> emac_variant/internal_phy > > > >>>>> So its not a problem. > > > >>>> > > > >>>> that is true as well, at least for now. > > > >>>> > > > >>>> So while I agree that having a separate property to indicate > > > >>>> the usage of the internal PHY would be nice, I am bit tempted > > > >>>> to use this easier approach and piggy back on the existing > > > >>>> phy-mode property. > > > >>> > > > >>> We're trying to fix an issue that works for now too. > > > >>> > > > >>> If we want to consider future weird cases, then we must > > > >>> consider all of them. And the phy mode changing is definitely > > > >>> not really far fetched. > > > >>> > > > >>> I agree with Chen-Yu, and I really feel like the compatible > > > >>> solution you suggested would cover both your concerns, and > > > >>> ours. > > > >> > > > >> So something like this? > > > >> emac: emac@1c30000 { > > > >> compatible = "allwinner,sun8i-h3-emac"; > > > >> ... > > > >> phy-mode = "mii"; > > > >> phy-handle = <&int_mii_phy>; > > > >> ... > > > >> > > > >> mdio: mdio { > > > >> #address-cells = <1>; > > > >> #size-cells = <0>; > > > >> int_mii_phy: ethernet-phy@1 { > > > >> compatible = "allwinner,sun8i-h3-ephy"; > > > >> syscon = <&syscon>; > > > > > > > > The MAC still needs to set some bits of syscon register. > > > > > > Yes, the syscon property needs also to be in the MAC node, that > > > was meant to be somewhere in the second "..." ;-) > > > > > > But now since Chen-Yu mentioned that we need to set up the PHY *first* > > > to make it actually discoverable via MDIO, I wonder if we could change > > > this to: > > > 1) have the DT as described here > > > 2) Let the dwmac-sun8i driver peek into the node referenced by > > > phy-handle and check the compatible string there. > > > 3) If that matches some allwinner internal PHY name, it sets up the PHY > > > to make it respond when the MDIO driver queries its bus. > > > > > > Or can a PHY driver set itself up (since we have clocks and resets > > > properties in there) *before* the MDIO bus gets scanned? > > > Chen-Yu's comment in the other mail hints at that this is not easily > > > possible. > > > > I think adding phy compatible just make things more complex. > > > > I think the patch series I sent early fix all problems without more > > complexity since: > > > > - it does not add more DT stuff > > - it use an already used in tree DT phy-mode "internal" (and so phy > > mode PHY_INTERFACE_MODE_INTERNAL) > > - it doesn't cover all the concerns we had > - it uses an undocumented value, with an unclear implication > The answer from Florian anyway breaks my logic, internal is for "internal phy with non-xMII protocol" not just internal PHY Regards
On 06/27/2017 10:29 AM, Maxime Ripard wrote: > On Tue, Jun 27, 2017 at 02:37:48PM +0200, Corentin Labbe wrote: >> On Tue, Jun 27, 2017 at 11:33:56AM +0100, Andre Przywara wrote: >>> Hi, >>> >>> On 27/06/17 11:23, Icenowy Zheng wrote: >>>> >>>> >>>> 于 2017年6月27日 GMT+08:00 下午6:15:58, Andre Przywara <andre.przywara@arm.com> 写到: >>>>> Hi, >>>>> >>>>> On 27/06/17 10:41, Maxime Ripard wrote: >>>>>> On Tue, Jun 27, 2017 at 10:02:45AM +0100, Andre Przywara wrote: >>>>>>> Hi, >>>>>>> >>>>>>> (CC:ing some people from that Rockchip dmwac series) >>>>>>> >>>>>>> On 27/06/17 09:21, Corentin Labbe wrote: >>>>>>>> On Tue, Jun 27, 2017 at 04:11:21PM +0800, Chen-Yu Tsai wrote: >>>>>>>>> On Tue, Jun 27, 2017 at 4:05 PM, Corentin Labbe >>>>>>>>> <clabbe.montjoie@gmail.com> wrote: >>>>>>>>>> On Mon, Jun 26, 2017 at 01:18:23AM +0100, André Przywara wrote: >>>>>>>>>>> On 31/05/17 08:18, Corentin Labbe wrote: >>>>>>>>>>>> The dwmac-sun8i is a heavy hacked version of stmmac hardware by >>>>>>>>>>>> allwinner. >>>>>>>>>>>> In fact the only common part is the descriptor management and >>>>> the first >>>>>>>>>>>> register function. >>>>>>>>>>> >>>>>>>>>>> Hi, >>>>>>>>>>> >>>>>>>>>>> I know I am a bit late with this, but while adapting the U-Boot >>>>> driver >>>>>>>>>>> to the new binding I was wondering about the internal PHY >>>>> detection: >>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>> So here you seem to deduce the usage of the internal PHY by the >>>>> PHY >>>>>>>>>>> interface specified in the DT (MII = internal, RGMII = >>>>> external). >>>>>>>>>>> I think I raised this question before, but isn't it perfectly >>>>> legal for >>>>>>>>>>> a board to use MII with an external PHY even on those SoCs that >>>>> feature >>>>>>>>>>> an internal PHY? >>>>>>>>>>> On the first glance that does not make too much sense, but apart >>>>> from >>>>>>>>>>> not being the correct binding to describe all of the SoCs >>>>> features I see >>>>>>>>>>> two scenarios: >>>>>>>>>>> 1) A board vendor might choose to not use the internal PHY >>>>> because it >>>>>>>>>>> has bugs, lacks features (configurability) or has other issues. >>>>> For >>>>>>>>>>> instance I have heard reports that the internal PHY makes the >>>>> SoC go >>>>>>>>>>> rather hot, possibly limiting the CPU frequency. By using an >>>>> external >>>>>>>>>>> MII PHY (which are still cheaper than RGMII PHYs) this can be >>>>> avoided. >>>>>>>>>>> 2) A PHY does not necessarily need to be directly connected to >>>>>>>>>>> magnetics. Indeed quite some boards use (RG)MII to connect to a >>>>> switch >>>>>>>>>>> IC or some other network circuitry, for instance fibre >>>>> connectors. >>>>>>>>>>> >>>>>>>>>>> So I was wondering if we would need an explicit: >>>>>>>>>>> allwinner,use-internal-phy; >>>>>>>>>>> boolean DT property to signal the usage of the internal PHY? >>>>>>>>>>> Alternatively we could go with the negative version: >>>>>>>>>>> allwinner,disable-internal-phy; >>>>>>>>>>> >>>>>>>>>>> Or what about introducing a new "allwinner,internal-mii-phy" >>>>> compatible >>>>>>>>>>> string for the *PHY* node and use that? >>>>>>>>>>> >>>>>>>>>>> I just want to avoid that we introduce a binding that causes us >>>>>>>>>>> headaches later. I think we can still fix this with a followup >>>>> patch >>>>>>>>>>> before the driver and its binding hit a release kernel. >>>>>>>>>>> >>>>>>>>>>> Cheers, >>>>>>>>>>> Andre. >>>>>>>>>>> >>>>>>>>>> >>>>>>>>>> I just see some patch, where "phy-mode = internal" is valid. >>>>>>>>>> I will try to find a way to use it >>>>>>>>> >>>>>>>>> Can you provide a link? >>>>>>>> >>>>>>>> https://lkml.org/lkml/2017/6/23/479 >>>>>>>> >>>>>>>>> >>>>>>>>> I'm not a fan of using phy-mode for this. There's no guarantee >>>>> what >>>>>>>>> mode the internal PHY uses. That's what phy-mode is for. >>>>>>> >>>>>>> I can understand Chen-Yu's concerns, but ... >>>>>>> >>>>>>>> For each soc the internal PHY mode is know and setted in >>>>> emac_variant/internal_phy >>>>>>>> So its not a problem. >>>>>>> >>>>>>> that is true as well, at least for now. >>>>>>> >>>>>>> So while I agree that having a separate property to indicate >>>>>>> the usage of the internal PHY would be nice, I am bit tempted >>>>>>> to use this easier approach and piggy back on the existing >>>>>>> phy-mode property. >>>>>> >>>>>> We're trying to fix an issue that works for now too. >>>>>> >>>>>> If we want to consider future weird cases, then we must >>>>>> consider all of them. And the phy mode changing is definitely >>>>>> not really far fetched. >>>>>> >>>>>> I agree with Chen-Yu, and I really feel like the compatible >>>>>> solution you suggested would cover both your concerns, and >>>>>> ours. >>>>> >>>>> So something like this? >>>>> emac: emac@1c30000 { >>>>> compatible = "allwinner,sun8i-h3-emac"; >>>>> ... >>>>> phy-mode = "mii"; >>>>> phy-handle = <&int_mii_phy>; >>>>> ... >>>>> >>>>> mdio: mdio { >>>>> #address-cells = <1>; >>>>> #size-cells = <0>; >>>>> int_mii_phy: ethernet-phy@1 { >>>>> compatible = "allwinner,sun8i-h3-ephy"; >>>>> syscon = <&syscon>; >>>> >>>> The MAC still needs to set some bits of syscon register. >>> >>> Yes, the syscon property needs also to be in the MAC node, that >>> was meant to be somewhere in the second "..." ;-) >>> >>> But now since Chen-Yu mentioned that we need to set up the PHY *first* >>> to make it actually discoverable via MDIO, I wonder if we could change >>> this to: >>> 1) have the DT as described here >>> 2) Let the dwmac-sun8i driver peek into the node referenced by >>> phy-handle and check the compatible string there. >>> 3) If that matches some allwinner internal PHY name, it sets up the PHY >>> to make it respond when the MDIO driver queries its bus. >>> >>> Or can a PHY driver set itself up (since we have clocks and resets >>> properties in there) *before* the MDIO bus gets scanned? >>> Chen-Yu's comment in the other mail hints at that this is not easily >>> possible. >> >> I think adding phy compatible just make things more complex. >> >> I think the patch series I sent early fix all problems without more >> complexity since: >> >> - it does not add more DT stuff >> - it use an already used in tree DT phy-mode "internal" (and so phy >> mode PHY_INTERFACE_MODE_INTERNAL) > > - it doesn't cover all the concerns we ha> - it uses an undocumented value, with an unclear implication No it's no longer undocumented since [1] https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git/commit/?id=29b65f5f97632722bb80969377e5b0e2401fb392 Due to the timezone difference, you guys have already managed to have several exchanges, hopefully I will have a chance to review your discussions a little later today.
On Tue, Jun 27, 2017 at 10:37:34AM -0700, Florian Fainelli wrote: > On 06/27/2017 10:29 AM, Maxime Ripard wrote: > > On Tue, Jun 27, 2017 at 02:37:48PM +0200, Corentin Labbe wrote: > >> On Tue, Jun 27, 2017 at 11:33:56AM +0100, Andre Przywara wrote: > >>> Hi, > >>> > >>> On 27/06/17 11:23, Icenowy Zheng wrote: > >>>> > >>>> > >>>> 于 2017年6月27日 GMT+08:00 下午6:15:58, Andre Przywara <andre.przywara@arm.com> 写到: > >>>>> Hi, > >>>>> > >>>>> On 27/06/17 10:41, Maxime Ripard wrote: > >>>>>> On Tue, Jun 27, 2017 at 10:02:45AM +0100, Andre Przywara wrote: > >>>>>>> Hi, > >>>>>>> > >>>>>>> (CC:ing some people from that Rockchip dmwac series) > >>>>>>> > >>>>>>> On 27/06/17 09:21, Corentin Labbe wrote: > >>>>>>>> On Tue, Jun 27, 2017 at 04:11:21PM +0800, Chen-Yu Tsai wrote: > >>>>>>>>> On Tue, Jun 27, 2017 at 4:05 PM, Corentin Labbe > >>>>>>>>> <clabbe.montjoie@gmail.com> wrote: > >>>>>>>>>> On Mon, Jun 26, 2017 at 01:18:23AM +0100, André Przywara wrote: > >>>>>>>>>>> On 31/05/17 08:18, Corentin Labbe wrote: > >>>>>>>>>>>> The dwmac-sun8i is a heavy hacked version of stmmac hardware by > >>>>>>>>>>>> allwinner. > >>>>>>>>>>>> In fact the only common part is the descriptor management and > >>>>> the first > >>>>>>>>>>>> register function. > >>>>>>>>>>> > >>>>>>>>>>> Hi, > >>>>>>>>>>> > >>>>>>>>>>> I know I am a bit late with this, but while adapting the U-Boot > >>>>> driver > >>>>>>>>>>> to the new binding I was wondering about the internal PHY > >>>>> detection: > >>>>>>>>>>> > >>>>>>>>>>> > >>>>>>>>>>> So here you seem to deduce the usage of the internal PHY by the > >>>>> PHY > >>>>>>>>>>> interface specified in the DT (MII = internal, RGMII = > >>>>> external). > >>>>>>>>>>> I think I raised this question before, but isn't it perfectly > >>>>> legal for > >>>>>>>>>>> a board to use MII with an external PHY even on those SoCs that > >>>>> feature > >>>>>>>>>>> an internal PHY? > >>>>>>>>>>> On the first glance that does not make too much sense, but apart > >>>>> from > >>>>>>>>>>> not being the correct binding to describe all of the SoCs > >>>>> features I see > >>>>>>>>>>> two scenarios: > >>>>>>>>>>> 1) A board vendor might choose to not use the internal PHY > >>>>> because it > >>>>>>>>>>> has bugs, lacks features (configurability) or has other issues. > >>>>> For > >>>>>>>>>>> instance I have heard reports that the internal PHY makes the > >>>>> SoC go > >>>>>>>>>>> rather hot, possibly limiting the CPU frequency. By using an > >>>>> external > >>>>>>>>>>> MII PHY (which are still cheaper than RGMII PHYs) this can be > >>>>> avoided. > >>>>>>>>>>> 2) A PHY does not necessarily need to be directly connected to > >>>>>>>>>>> magnetics. Indeed quite some boards use (RG)MII to connect to a > >>>>> switch > >>>>>>>>>>> IC or some other network circuitry, for instance fibre > >>>>> connectors. > >>>>>>>>>>> > >>>>>>>>>>> So I was wondering if we would need an explicit: > >>>>>>>>>>> allwinner,use-internal-phy; > >>>>>>>>>>> boolean DT property to signal the usage of the internal PHY? > >>>>>>>>>>> Alternatively we could go with the negative version: > >>>>>>>>>>> allwinner,disable-internal-phy; > >>>>>>>>>>> > >>>>>>>>>>> Or what about introducing a new "allwinner,internal-mii-phy" > >>>>> compatible > >>>>>>>>>>> string for the *PHY* node and use that? > >>>>>>>>>>> > >>>>>>>>>>> I just want to avoid that we introduce a binding that causes us > >>>>>>>>>>> headaches later. I think we can still fix this with a followup > >>>>> patch > >>>>>>>>>>> before the driver and its binding hit a release kernel. > >>>>>>>>>>> > >>>>>>>>>>> Cheers, > >>>>>>>>>>> Andre. > >>>>>>>>>>> > >>>>>>>>>> > >>>>>>>>>> I just see some patch, where "phy-mode = internal" is valid. > >>>>>>>>>> I will try to find a way to use it > >>>>>>>>> > >>>>>>>>> Can you provide a link? > >>>>>>>> > >>>>>>>> https://lkml.org/lkml/2017/6/23/479 > >>>>>>>> > >>>>>>>>> > >>>>>>>>> I'm not a fan of using phy-mode for this. There's no guarantee > >>>>> what > >>>>>>>>> mode the internal PHY uses. That's what phy-mode is for. > >>>>>>> > >>>>>>> I can understand Chen-Yu's concerns, but ... > >>>>>>> > >>>>>>>> For each soc the internal PHY mode is know and setted in > >>>>> emac_variant/internal_phy > >>>>>>>> So its not a problem. > >>>>>>> > >>>>>>> that is true as well, at least for now. > >>>>>>> > >>>>>>> So while I agree that having a separate property to indicate > >>>>>>> the usage of the internal PHY would be nice, I am bit tempted > >>>>>>> to use this easier approach and piggy back on the existing > >>>>>>> phy-mode property. > >>>>>> > >>>>>> We're trying to fix an issue that works for now too. > >>>>>> > >>>>>> If we want to consider future weird cases, then we must > >>>>>> consider all of them. And the phy mode changing is definitely > >>>>>> not really far fetched. > >>>>>> > >>>>>> I agree with Chen-Yu, and I really feel like the compatible > >>>>>> solution you suggested would cover both your concerns, and > >>>>>> ours. > >>>>> > >>>>> So something like this? > >>>>> emac: emac@1c30000 { > >>>>> compatible = "allwinner,sun8i-h3-emac"; > >>>>> ... > >>>>> phy-mode = "mii"; > >>>>> phy-handle = <&int_mii_phy>; > >>>>> ... > >>>>> > >>>>> mdio: mdio { > >>>>> #address-cells = <1>; > >>>>> #size-cells = <0>; > >>>>> int_mii_phy: ethernet-phy@1 { > >>>>> compatible = "allwinner,sun8i-h3-ephy"; > >>>>> syscon = <&syscon>; > >>>> > >>>> The MAC still needs to set some bits of syscon register. > >>> > >>> Yes, the syscon property needs also to be in the MAC node, that > >>> was meant to be somewhere in the second "..." ;-) > >>> > >>> But now since Chen-Yu mentioned that we need to set up the PHY *first* > >>> to make it actually discoverable via MDIO, I wonder if we could change > >>> this to: > >>> 1) have the DT as described here > >>> 2) Let the dwmac-sun8i driver peek into the node referenced by > >>> phy-handle and check the compatible string there. > >>> 3) If that matches some allwinner internal PHY name, it sets up the PHY > >>> to make it respond when the MDIO driver queries its bus. > >>> > >>> Or can a PHY driver set itself up (since we have clocks and resets > >>> properties in there) *before* the MDIO bus gets scanned? > >>> Chen-Yu's comment in the other mail hints at that this is not easily > >>> possible. > >> > >> I think adding phy compatible just make things more complex. > >> > >> I think the patch series I sent early fix all problems without more > >> complexity since: > >> > >> - it does not add more DT stuff > >> - it use an already used in tree DT phy-mode "internal" (and so phy > >> mode PHY_INTERFACE_MODE_INTERNAL) > > > > - it doesn't cover all the concerns we ha> - it uses an undocumented value, with an unclear implication > > No it's no longer undocumented since [1] > > https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git/commit/?id=29b65f5f97632722bb80969377e5b0e2401fb392 > > Due to the timezone difference, you guys have already managed to have > several exchanges, hopefully I will have a chance to review your > discussions a little later today. Hello I wait for your comment before sending my reverts patch for http://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1431579.html Could you confirm that internal is only meant for "non xMII internal protocol" Regards
On 30/06/2017 23:53, Corentin Labbe wrote: > On Tue, Jun 27, 2017 at 10:37:34AM -0700, Florian Fainelli wrote: >> On 06/27/2017 10:29 AM, Maxime Ripard wrote: >>> On Tue, Jun 27, 2017 at 02:37:48PM +0200, Corentin Labbe wrote: >>>> On Tue, Jun 27, 2017 at 11:33:56AM +0100, Andre Przywara wrote: >>>>> Hi, >>>>> >>>>> On 27/06/17 11:23, Icenowy Zheng wrote: >>>>>> >>>>>> >>>>>> 于 2017年6月27日 GMT+08:00 下午6:15:58, Andre Przywara <andre.przywara@arm.com> 写到: >>>>>>> Hi, >>>>>>> >>>>>>> On 27/06/17 10:41, Maxime Ripard wrote: >>>>>>>> On Tue, Jun 27, 2017 at 10:02:45AM +0100, Andre Przywara wrote: >>>>>>>>> Hi, >>>>>>>>> >>>>>>>>> (CC:ing some people from that Rockchip dmwac series) >>>>>>>>> >>>>>>>>> On 27/06/17 09:21, Corentin Labbe wrote: >>>>>>>>>> On Tue, Jun 27, 2017 at 04:11:21PM +0800, Chen-Yu Tsai wrote: >>>>>>>>>>> On Tue, Jun 27, 2017 at 4:05 PM, Corentin Labbe >>>>>>>>>>> <clabbe.montjoie@gmail.com> wrote: >>>>>>>>>>>> On Mon, Jun 26, 2017 at 01:18:23AM +0100, André Przywara wrote: >>>>>>>>>>>>> On 31/05/17 08:18, Corentin Labbe wrote: >>>>>>>>>>>>>> The dwmac-sun8i is a heavy hacked version of stmmac hardware by >>>>>>>>>>>>>> allwinner. >>>>>>>>>>>>>> In fact the only common part is the descriptor management and >>>>>>> the first >>>>>>>>>>>>>> register function. >>>>>>>>>>>>> >>>>>>>>>>>>> Hi, >>>>>>>>>>>>> >>>>>>>>>>>>> I know I am a bit late with this, but while adapting the U-Boot >>>>>>> driver >>>>>>>>>>>>> to the new binding I was wondering about the internal PHY >>>>>>> detection: >>>>>>>>>>>>> >>>>>>>>>>>>> >>>>>>>>>>>>> So here you seem to deduce the usage of the internal PHY by the >>>>>>> PHY >>>>>>>>>>>>> interface specified in the DT (MII = internal, RGMII = >>>>>>> external). >>>>>>>>>>>>> I think I raised this question before, but isn't it perfectly >>>>>>> legal for >>>>>>>>>>>>> a board to use MII with an external PHY even on those SoCs that >>>>>>> feature >>>>>>>>>>>>> an internal PHY? >>>>>>>>>>>>> On the first glance that does not make too much sense, but apart >>>>>>> from >>>>>>>>>>>>> not being the correct binding to describe all of the SoCs >>>>>>> features I see >>>>>>>>>>>>> two scenarios: >>>>>>>>>>>>> 1) A board vendor might choose to not use the internal PHY >>>>>>> because it >>>>>>>>>>>>> has bugs, lacks features (configurability) or has other issues. >>>>>>> For >>>>>>>>>>>>> instance I have heard reports that the internal PHY makes the >>>>>>> SoC go >>>>>>>>>>>>> rather hot, possibly limiting the CPU frequency. By using an >>>>>>> external >>>>>>>>>>>>> MII PHY (which are still cheaper than RGMII PHYs) this can be >>>>>>> avoided. >>>>>>>>>>>>> 2) A PHY does not necessarily need to be directly connected to >>>>>>>>>>>>> magnetics. Indeed quite some boards use (RG)MII to connect to a >>>>>>> switch >>>>>>>>>>>>> IC or some other network circuitry, for instance fibre >>>>>>> connectors. >>>>>>>>>>>>> >>>>>>>>>>>>> So I was wondering if we would need an explicit: >>>>>>>>>>>>> allwinner,use-internal-phy; >>>>>>>>>>>>> boolean DT property to signal the usage of the internal PHY? >>>>>>>>>>>>> Alternatively we could go with the negative version: >>>>>>>>>>>>> allwinner,disable-internal-phy; >>>>>>>>>>>>> >>>>>>>>>>>>> Or what about introducing a new "allwinner,internal-mii-phy" >>>>>>> compatible >>>>>>>>>>>>> string for the *PHY* node and use that? >>>>>>>>>>>>> >>>>>>>>>>>>> I just want to avoid that we introduce a binding that causes us >>>>>>>>>>>>> headaches later. I think we can still fix this with a followup >>>>>>> patch >>>>>>>>>>>>> before the driver and its binding hit a release kernel. >>>>>>>>>>>>> >>>>>>>>>>>>> Cheers, >>>>>>>>>>>>> Andre. >>>>>>>>>>>>> >>>>>>>>>>>> >>>>>>>>>>>> I just see some patch, where "phy-mode = internal" is valid. >>>>>>>>>>>> I will try to find a way to use it >>>>>>>>>>> >>>>>>>>>>> Can you provide a link? >>>>>>>>>> >>>>>>>>>> https://lkml.org/lkml/2017/6/23/479 >>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>> I'm not a fan of using phy-mode for this. There's no guarantee >>>>>>> what >>>>>>>>>>> mode the internal PHY uses. That's what phy-mode is for. >>>>>>>>> >>>>>>>>> I can understand Chen-Yu's concerns, but ... >>>>>>>>> >>>>>>>>>> For each soc the internal PHY mode is know and setted in >>>>>>> emac_variant/internal_phy >>>>>>>>>> So its not a problem. >>>>>>>>> >>>>>>>>> that is true as well, at least for now. >>>>>>>>> >>>>>>>>> So while I agree that having a separate property to indicate >>>>>>>>> the usage of the internal PHY would be nice, I am bit tempted >>>>>>>>> to use this easier approach and piggy back on the existing >>>>>>>>> phy-mode property. >>>>>>>> >>>>>>>> We're trying to fix an issue that works for now too. >>>>>>>> >>>>>>>> If we want to consider future weird cases, then we must >>>>>>>> consider all of them. And the phy mode changing is definitely >>>>>>>> not really far fetched. >>>>>>>> >>>>>>>> I agree with Chen-Yu, and I really feel like the compatible >>>>>>>> solution you suggested would cover both your concerns, and >>>>>>>> ours. >>>>>>> >>>>>>> So something like this? >>>>>>> emac: emac@1c30000 { >>>>>>> compatible = "allwinner,sun8i-h3-emac"; >>>>>>> ... >>>>>>> phy-mode = "mii"; >>>>>>> phy-handle = <&int_mii_phy>; >>>>>>> ... >>>>>>> >>>>>>> mdio: mdio { >>>>>>> #address-cells = <1>; >>>>>>> #size-cells = <0>; >>>>>>> int_mii_phy: ethernet-phy@1 { >>>>>>> compatible = "allwinner,sun8i-h3-ephy"; >>>>>>> syscon = <&syscon>; >>>>>> >>>>>> The MAC still needs to set some bits of syscon register. >>>>> >>>>> Yes, the syscon property needs also to be in the MAC node, that >>>>> was meant to be somewhere in the second "..." ;-) >>>>> >>>>> But now since Chen-Yu mentioned that we need to set up the PHY *first* >>>>> to make it actually discoverable via MDIO, I wonder if we could change >>>>> this to: >>>>> 1) have the DT as described here >>>>> 2) Let the dwmac-sun8i driver peek into the node referenced by >>>>> phy-handle and check the compatible string there. >>>>> 3) If that matches some allwinner internal PHY name, it sets up the PHY >>>>> to make it respond when the MDIO driver queries its bus. >>>>> >>>>> Or can a PHY driver set itself up (since we have clocks and resets >>>>> properties in there) *before* the MDIO bus gets scanned? >>>>> Chen-Yu's comment in the other mail hints at that this is not easily >>>>> possible. >>>> >>>> I think adding phy compatible just make things more complex. >>>> >>>> I think the patch series I sent early fix all problems without more >>>> complexity since: >>>> >>>> - it does not add more DT stuff >>>> - it use an already used in tree DT phy-mode "internal" (and so phy >>>> mode PHY_INTERFACE_MODE_INTERNAL) >>> >>> - it doesn't cover all the concerns we ha> - it uses an undocumented value, with an unclear implication >> >> No it's no longer undocumented since [1] >> >> https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git/commit/?id=29b65f5f97632722bb80969377e5b0e2401fb392 >> >> Due to the timezone difference, you guys have already managed to have >> several exchanges, hopefully I will have a chance to review your >> discussions a little later today. > > Hello > > I wait for your comment before sending my reverts patch for http://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1431579.html > Could you confirm that internal is only meant for "non xMII internal protocol" Yes that's what is it meant for. There are possibly two ways here: 1) assuming there is already a specific PHY driver for that internal PHY, you should have this PHY driver set PHY_IS_INTERNAL (see bcm63xx.c and bcm7xxx.c that do that) and so you would know that you did bind to the correct internal PHY driver. Problem with that is if you need to perform a particular action such that you will successfully bind to the internal PHY (e.g: power on, reset, etc.) 2) We could create a new set of phy-mode values that are, e.g: 'internal-mii': internal MII connection to the PHY and so on in order to cover the internal variants of those modes. I am not sure this is strictly needed here though. -- Florian
On Sat, Jul 01, 2017 at 02:42:14PM -0700, Florian Fainelli wrote: > On 30/06/2017 23:53, Corentin Labbe wrote: > > On Tue, Jun 27, 2017 at 10:37:34AM -0700, Florian Fainelli wrote: > >> On 06/27/2017 10:29 AM, Maxime Ripard wrote: > >>> On Tue, Jun 27, 2017 at 02:37:48PM +0200, Corentin Labbe wrote: > >>>> On Tue, Jun 27, 2017 at 11:33:56AM +0100, Andre Przywara wrote: > >>>>> Hi, > >>>>> > >>>>> On 27/06/17 11:23, Icenowy Zheng wrote: > >>>>>> > >>>>>> > >>>>>> 于 2017年6月27日 GMT+08:00 下午6:15:58, Andre Przywara <andre.przywara@arm.com> 写到: > >>>>>>> Hi, > >>>>>>> > >>>>>>> On 27/06/17 10:41, Maxime Ripard wrote: > >>>>>>>> On Tue, Jun 27, 2017 at 10:02:45AM +0100, Andre Przywara wrote: > >>>>>>>>> Hi, > >>>>>>>>> > >>>>>>>>> (CC:ing some people from that Rockchip dmwac series) > >>>>>>>>> > >>>>>>>>> On 27/06/17 09:21, Corentin Labbe wrote: > >>>>>>>>>> On Tue, Jun 27, 2017 at 04:11:21PM +0800, Chen-Yu Tsai wrote: > >>>>>>>>>>> On Tue, Jun 27, 2017 at 4:05 PM, Corentin Labbe > >>>>>>>>>>> <clabbe.montjoie@gmail.com> wrote: > >>>>>>>>>>>> On Mon, Jun 26, 2017 at 01:18:23AM +0100, André Przywara wrote: > >>>>>>>>>>>>> On 31/05/17 08:18, Corentin Labbe wrote: > >>>>>>>>>>>>>> The dwmac-sun8i is a heavy hacked version of stmmac hardware by > >>>>>>>>>>>>>> allwinner. > >>>>>>>>>>>>>> In fact the only common part is the descriptor management and > >>>>>>> the first > >>>>>>>>>>>>>> register function. > >>>>>>>>>>>>> > >>>>>>>>>>>>> Hi, > >>>>>>>>>>>>> > >>>>>>>>>>>>> I know I am a bit late with this, but while adapting the U-Boot > >>>>>>> driver > >>>>>>>>>>>>> to the new binding I was wondering about the internal PHY > >>>>>>> detection: > >>>>>>>>>>>>> > >>>>>>>>>>>>> > >>>>>>>>>>>>> So here you seem to deduce the usage of the internal PHY by the > >>>>>>> PHY > >>>>>>>>>>>>> interface specified in the DT (MII = internal, RGMII = > >>>>>>> external). > >>>>>>>>>>>>> I think I raised this question before, but isn't it perfectly > >>>>>>> legal for > >>>>>>>>>>>>> a board to use MII with an external PHY even on those SoCs that > >>>>>>> feature > >>>>>>>>>>>>> an internal PHY? > >>>>>>>>>>>>> On the first glance that does not make too much sense, but apart > >>>>>>> from > >>>>>>>>>>>>> not being the correct binding to describe all of the SoCs > >>>>>>> features I see > >>>>>>>>>>>>> two scenarios: > >>>>>>>>>>>>> 1) A board vendor might choose to not use the internal PHY > >>>>>>> because it > >>>>>>>>>>>>> has bugs, lacks features (configurability) or has other issues. > >>>>>>> For > >>>>>>>>>>>>> instance I have heard reports that the internal PHY makes the > >>>>>>> SoC go > >>>>>>>>>>>>> rather hot, possibly limiting the CPU frequency. By using an > >>>>>>> external > >>>>>>>>>>>>> MII PHY (which are still cheaper than RGMII PHYs) this can be > >>>>>>> avoided. > >>>>>>>>>>>>> 2) A PHY does not necessarily need to be directly connected to > >>>>>>>>>>>>> magnetics. Indeed quite some boards use (RG)MII to connect to a > >>>>>>> switch > >>>>>>>>>>>>> IC or some other network circuitry, for instance fibre > >>>>>>> connectors. > >>>>>>>>>>>>> > >>>>>>>>>>>>> So I was wondering if we would need an explicit: > >>>>>>>>>>>>> allwinner,use-internal-phy; > >>>>>>>>>>>>> boolean DT property to signal the usage of the internal PHY? > >>>>>>>>>>>>> Alternatively we could go with the negative version: > >>>>>>>>>>>>> allwinner,disable-internal-phy; > >>>>>>>>>>>>> > >>>>>>>>>>>>> Or what about introducing a new "allwinner,internal-mii-phy" > >>>>>>> compatible > >>>>>>>>>>>>> string for the *PHY* node and use that? > >>>>>>>>>>>>> > >>>>>>>>>>>>> I just want to avoid that we introduce a binding that causes us > >>>>>>>>>>>>> headaches later. I think we can still fix this with a followup > >>>>>>> patch > >>>>>>>>>>>>> before the driver and its binding hit a release kernel. > >>>>>>>>>>>>> > >>>>>>>>>>>>> Cheers, > >>>>>>>>>>>>> Andre. > >>>>>>>>>>>>> > >>>>>>>>>>>> > >>>>>>>>>>>> I just see some patch, where "phy-mode = internal" is valid. > >>>>>>>>>>>> I will try to find a way to use it > >>>>>>>>>>> > >>>>>>>>>>> Can you provide a link? > >>>>>>>>>> > >>>>>>>>>> https://lkml.org/lkml/2017/6/23/479 > >>>>>>>>>> > >>>>>>>>>>> > >>>>>>>>>>> I'm not a fan of using phy-mode for this. There's no guarantee > >>>>>>> what > >>>>>>>>>>> mode the internal PHY uses. That's what phy-mode is for. > >>>>>>>>> > >>>>>>>>> I can understand Chen-Yu's concerns, but ... > >>>>>>>>> > >>>>>>>>>> For each soc the internal PHY mode is know and setted in > >>>>>>> emac_variant/internal_phy > >>>>>>>>>> So its not a problem. > >>>>>>>>> > >>>>>>>>> that is true as well, at least for now. > >>>>>>>>> > >>>>>>>>> So while I agree that having a separate property to indicate > >>>>>>>>> the usage of the internal PHY would be nice, I am bit tempted > >>>>>>>>> to use this easier approach and piggy back on the existing > >>>>>>>>> phy-mode property. > >>>>>>>> > >>>>>>>> We're trying to fix an issue that works for now too. > >>>>>>>> > >>>>>>>> If we want to consider future weird cases, then we must > >>>>>>>> consider all of them. And the phy mode changing is definitely > >>>>>>>> not really far fetched. > >>>>>>>> > >>>>>>>> I agree with Chen-Yu, and I really feel like the compatible > >>>>>>>> solution you suggested would cover both your concerns, and > >>>>>>>> ours. > >>>>>>> > >>>>>>> So something like this? > >>>>>>> emac: emac@1c30000 { > >>>>>>> compatible = "allwinner,sun8i-h3-emac"; > >>>>>>> ... > >>>>>>> phy-mode = "mii"; > >>>>>>> phy-handle = <&int_mii_phy>; > >>>>>>> ... > >>>>>>> > >>>>>>> mdio: mdio { > >>>>>>> #address-cells = <1>; > >>>>>>> #size-cells = <0>; > >>>>>>> int_mii_phy: ethernet-phy@1 { > >>>>>>> compatible = "allwinner,sun8i-h3-ephy"; > >>>>>>> syscon = <&syscon>; > >>>>>> > >>>>>> The MAC still needs to set some bits of syscon register. > >>>>> > >>>>> Yes, the syscon property needs also to be in the MAC node, that > >>>>> was meant to be somewhere in the second "..." ;-) > >>>>> > >>>>> But now since Chen-Yu mentioned that we need to set up the PHY *first* > >>>>> to make it actually discoverable via MDIO, I wonder if we could change > >>>>> this to: > >>>>> 1) have the DT as described here > >>>>> 2) Let the dwmac-sun8i driver peek into the node referenced by > >>>>> phy-handle and check the compatible string there. > >>>>> 3) If that matches some allwinner internal PHY name, it sets up the PHY > >>>>> to make it respond when the MDIO driver queries its bus. > >>>>> > >>>>> Or can a PHY driver set itself up (since we have clocks and resets > >>>>> properties in there) *before* the MDIO bus gets scanned? > >>>>> Chen-Yu's comment in the other mail hints at that this is not easily > >>>>> possible. > >>>> > >>>> I think adding phy compatible just make things more complex. > >>>> > >>>> I think the patch series I sent early fix all problems without more > >>>> complexity since: > >>>> > >>>> - it does not add more DT stuff > >>>> - it use an already used in tree DT phy-mode "internal" (and so phy > >>>> mode PHY_INTERFACE_MODE_INTERNAL) > >>> > >>> - it doesn't cover all the concerns we ha> - it uses an undocumented value, with an unclear implication > >> > >> No it's no longer undocumented since [1] > >> > >> https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git/commit/?id=29b65f5f97632722bb80969377e5b0e2401fb392 > >> > >> Due to the timezone difference, you guys have already managed to have > >> several exchanges, hopefully I will have a chance to review your > >> discussions a little later today. > > > > Hello > > > > I wait for your comment before sending my reverts patch for http://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1431579.html > > Could you confirm that internal is only meant for "non xMII internal protocol" > > Yes that's what is it meant for. There are possibly two ways here: > > 1) assuming there is already a specific PHY driver for that internal > PHY, you should have this PHY driver set PHY_IS_INTERNAL (see bcm63xx.c > and bcm7xxx.c that do that) and so you would know that you did bind to > the correct internal PHY driver. Problem with that is if you need to > perform a particular action such that you will successfully bind to the > internal PHY (e.g: power on, reset, etc.) > > 2) We could create a new set of phy-mode values that are, e.g: > > 'internal-mii': internal MII connection to the PHY > > and so on in order to cover the internal variants of those modes. I am > not sure this is strictly needed here though. Or perhaps a phy-location = "external|internal" ?
diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig index cfbe3634dfa1..85c0e41f8021 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -145,6 +145,17 @@ config DWMAC_SUNXI This selects Allwinner SoC glue layer support for the stmmac device driver. This driver is used for A20/A31 GMAC ethernet controller. + +config DWMAC_SUN8I + tristate "Allwinner sun8i GMAC support" + default ARCH_SUNXI + depends on OF && (ARCH_SUNXI || COMPILE_TEST) + ---help--- + Support for Allwinner H3 A83T A64 EMAC ethernet controllers. + + This selects Allwinner SoC glue layer support for the + stmmac device driver. This driver is used for H3/A83T/A64 + EMAC ethernet controller. endif config STMMAC_PCI diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile index 700c60336674..fd4937a7fcab 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_DWMAC_SOCFPGA) += dwmac-altr-socfpga.o obj-$(CONFIG_DWMAC_STI) += dwmac-sti.o obj-$(CONFIG_DWMAC_STM32) += dwmac-stm32.o obj-$(CONFIG_DWMAC_SUNXI) += dwmac-sunxi.o +obj-$(CONFIG_DWMAC_SUN8I) += dwmac-sun8i.o obj-$(CONFIG_DWMAC_DWC_QOS_ETH) += dwmac-dwc-qos-eth.o obj-$(CONFIG_DWMAC_GENERIC) += dwmac-generic.o stmmac-platform-objs:= stmmac_platform.o diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c new file mode 100644 index 000000000000..1a6bfe6c958f --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c @@ -0,0 +1,990 @@ +/* + * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer + * + * Copyright (C) 2017 Corentin Labbe <clabbe.montjoie@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/iopoll.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/of_mdio.h> +#include <linux/of_net.h> +#include <linux/phy.h> +#include <linux/platform_device.h> +#include <linux/regulator/consumer.h> +#include <linux/regmap.h> +#include <linux/stmmac.h> + +#include "stmmac.h" +#include "stmmac_platform.h" + +/* General notes on dwmac-sun8i: + * Locking: no locking is necessary in this file because all necessary locking + * is done in the "stmmac files" + */ + +/* struct emac_variant - Descrive dwmac-sun8i hardware variant + * @default_syscon_value: The default value of the EMAC register in syscon + * This value is used for disabling properly EMAC + * and used as a good starting value in case of the + * boot process(uboot) leave some stuff. + * @internal_phy: Does the MAC embed an internal PHY + * @support_mii: Does the MAC handle MII + * @support_rmii: Does the MAC handle RMII + * @support_rgmii: Does the MAC handle RGMII + */ +struct emac_variant { + u32 default_syscon_value; + int internal_phy; + bool support_mii; + bool support_rmii; + bool support_rgmii; +}; + +/* struct sunxi_priv_data - hold all sunxi private data + * @tx_clk: reference to MAC TX clock + * @ephy_clk: reference to the optional EPHY clock for the internal PHY + * @regulator: reference to the optional regulator + * @rst_ephy: reference to the optional EPHY reset for the internal PHY + * @variant: reference to the current board variant + * @regmap: regmap for using the syscon + * @use_internal_phy: Does the current PHY choice imply using the internal PHY + */ +struct sunxi_priv_data { + struct clk *tx_clk; + struct clk *ephy_clk; + struct regulator *regulator; + struct reset_control *rst_ephy; + const struct emac_variant *variant; + struct regmap *regmap; + bool use_internal_phy; +}; + +static const struct emac_variant emac_variant_h3 = { + .default_syscon_value = 0x58000, + .internal_phy = PHY_INTERFACE_MODE_MII, + .support_mii = true, + .support_rmii = true, + .support_rgmii = true +}; + +static const struct emac_variant emac_variant_a83t = { + .default_syscon_value = 0, + .internal_phy = 0, + .support_mii = true, + .support_rgmii = true +}; + +static const struct emac_variant emac_variant_a64 = { + .default_syscon_value = 0, + .internal_phy = 0, + .support_mii = true, + .support_rmii = true, + .support_rgmii = true +}; + +#define EMAC_BASIC_CTL0 0x00 +#define EMAC_BASIC_CTL1 0x04 +#define EMAC_INT_STA 0x08 +#define EMAC_INT_EN 0x0C +#define EMAC_TX_CTL0 0x10 +#define EMAC_TX_CTL1 0x14 +#define EMAC_TX_FLOW_CTL 0x1C +#define EMAC_TX_DESC_LIST 0x20 +#define EMAC_RX_CTL0 0x24 +#define EMAC_RX_CTL1 0x28 +#define EMAC_RX_DESC_LIST 0x34 +#define EMAC_RX_FRM_FLT 0x38 +#define EMAC_MDIO_CMD 0x48 +#define EMAC_MDIO_DATA 0x4C +#define EMAC_MACADDR_HI(reg) (0x50 + (reg) * 8) +#define EMAC_MACADDR_LO(reg) (0x54 + (reg) * 8) +#define EMAC_TX_DMA_STA 0xB0 +#define EMAC_TX_CUR_DESC 0xB4 +#define EMAC_TX_CUR_BUF 0xB8 +#define EMAC_RX_DMA_STA 0xC0 +#define EMAC_RX_CUR_DESC 0xC4 +#define EMAC_RX_CUR_BUF 0xC8 + +/* Use in EMAC_BASIC_CTL0 */ +#define EMAC_DUPLEX_FULL BIT(0) +#define EMAC_LOOPBACK BIT(1) +#define EMAC_SPEED_1000 0 +#define EMAC_SPEED_100 (0x03 << 2) +#define EMAC_SPEED_10 (0x02 << 2) + +/* Use in EMAC_BASIC_CTL1 */ +#define EMAC_BURSTLEN_SHIFT 24 + +/* Used in EMAC_RX_FRM_FLT */ +#define EMAC_FRM_FLT_RXALL BIT(0) +#define EMAC_FRM_FLT_CTL BIT(13) +#define EMAC_FRM_FLT_MULTICAST BIT(16) + +/* Used in RX_CTL1*/ +#define EMAC_RX_MD BIT(1) +#define EMAC_RX_TH_MASK GENMASK(4, 5) +#define EMAC_RX_TH_32 0 +#define EMAC_RX_TH_64 (0x1 << 4) +#define EMAC_RX_TH_96 (0x2 << 4) +#define EMAC_RX_TH_128 (0x3 << 4) +#define EMAC_RX_DMA_EN BIT(30) +#define EMAC_RX_DMA_START BIT(31) + +/* Used in TX_CTL1*/ +#define EMAC_TX_MD BIT(1) +#define EMAC_TX_NEXT_FRM BIT(2) +#define EMAC_TX_TH_MASK GENMASK(8, 10) +#define EMAC_TX_TH_64 0 +#define EMAC_TX_TH_128 (0x1 << 8) +#define EMAC_TX_TH_192 (0x2 << 8) +#define EMAC_TX_TH_256 (0x3 << 8) +#define EMAC_TX_DMA_EN BIT(30) +#define EMAC_TX_DMA_START BIT(31) + +/* Used in RX_CTL0 */ +#define EMAC_RX_RECEIVER_EN BIT(31) +#define EMAC_RX_DO_CRC BIT(27) +#define EMAC_RX_FLOW_CTL_EN BIT(16) + +/* Used in TX_CTL0 */ +#define EMAC_TX_TRANSMITTER_EN BIT(31) + +/* Used in EMAC_TX_FLOW_CTL */ +#define EMAC_TX_FLOW_CTL_EN BIT(0) + +/* Used in EMAC_INT_STA */ +#define EMAC_TX_INT BIT(0) +#define EMAC_TX_DMA_STOP_INT BIT(1) +#define EMAC_TX_BUF_UA_INT BIT(2) +#define EMAC_TX_TIMEOUT_INT BIT(3) +#define EMAC_TX_UNDERFLOW_INT BIT(4) +#define EMAC_TX_EARLY_INT BIT(5) +#define EMAC_RX_INT BIT(8) +#define EMAC_RX_BUF_UA_INT BIT(9) +#define EMAC_RX_DMA_STOP_INT BIT(10) +#define EMAC_RX_TIMEOUT_INT BIT(11) +#define EMAC_RX_OVERFLOW_INT BIT(12) +#define EMAC_RX_EARLY_INT BIT(13) +#define EMAC_RGMII_STA_INT BIT(16) + +#define MAC_ADDR_TYPE_DST BIT(31) + +/* H3 specific bits for EPHY */ +#define H3_EPHY_ADDR_SHIFT 20 +#define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */ +#define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */ +#define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */ + +/* H3/A64 specific bits */ +#define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */ + +/* Generic system control EMAC_CLK bits */ +#define SYSCON_ETXDC_MASK GENMASK(2, 0) +#define SYSCON_ETXDC_SHIFT 10 +#define SYSCON_ERXDC_MASK GENMASK(4, 0) +#define SYSCON_ERXDC_SHIFT 5 +/* EMAC PHY Interface Type */ +#define SYSCON_EPIT BIT(2) /* 1: RGMII, 0: MII */ +#define SYSCON_ETCS_MASK GENMASK(1, 0) +#define SYSCON_ETCS_MII 0x0 +#define SYSCON_ETCS_EXT_GMII 0x1 +#define SYSCON_ETCS_INT_GMII 0x2 +#define SYSCON_EMAC_REG 0x30 + +/* sun8i_dwmac_dma_reset() - reset the EMAC + * Called from stmmac via stmmac_dma_ops->reset + */ +static int sun8i_dwmac_dma_reset(void __iomem *ioaddr) +{ + writel(0, ioaddr + EMAC_RX_CTL1); + writel(0, ioaddr + EMAC_TX_CTL1); + writel(0, ioaddr + EMAC_RX_FRM_FLT); + writel(0, ioaddr + EMAC_RX_DESC_LIST); + writel(0, ioaddr + EMAC_TX_DESC_LIST); + writel(0, ioaddr + EMAC_INT_EN); + writel(0x1FFFFFF, ioaddr + EMAC_INT_STA); + return 0; +} + +/* sun8i_dwmac_dma_init() - initialize the EMAC + * Called from stmmac via stmmac_dma_ops->init + */ +static void sun8i_dwmac_dma_init(void __iomem *ioaddr, + struct stmmac_dma_cfg *dma_cfg, + u32 dma_tx, u32 dma_rx, int atds) +{ + /* Write TX and RX descriptors address */ + writel(dma_rx, ioaddr + EMAC_RX_DESC_LIST); + writel(dma_tx, ioaddr + EMAC_TX_DESC_LIST); + + writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN); + writel(0x1FFFFFF, ioaddr + EMAC_INT_STA); +} + +/* sun8i_dwmac_dump_regs() - Dump EMAC address space + * Called from stmmac_dma_ops->dump_regs + * Used for ethtool + */ +static void sun8i_dwmac_dump_regs(void __iomem *ioaddr, u32 *reg_space) +{ + int i; + + for (i = 0; i < 0xC8; i += 4) { + if (i == 0x32 || i == 0x3C) + continue; + reg_space[i / 4] = readl(ioaddr + i); + } +} + +/* sun8i_dwmac_dump_mac_regs() - Dump EMAC address space + * Called from stmmac_ops->dump_regs + * Used for ethtool + */ +static void sun8i_dwmac_dump_mac_regs(struct mac_device_info *hw, + u32 *reg_space) +{ + int i; + void __iomem *ioaddr = hw->pcsr; + + for (i = 0; i < 0xC8; i += 4) { + if (i == 0x32 || i == 0x3C) + continue; + reg_space[i / 4] = readl(ioaddr + i); + } +} + +static void sun8i_dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan) +{ + writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN); +} + +static void sun8i_dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan) +{ + writel(0, ioaddr + EMAC_INT_EN); +} + +static void sun8i_dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan) +{ + u32 v; + + v = readl(ioaddr + EMAC_TX_CTL1); + v |= EMAC_TX_DMA_START; + v |= EMAC_TX_DMA_EN; + writel(v, ioaddr + EMAC_TX_CTL1); +} + +static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr) +{ + u32 v; + + v = readl(ioaddr + EMAC_TX_CTL1); + v |= EMAC_TX_DMA_START; + v |= EMAC_TX_DMA_EN; + writel(v, ioaddr + EMAC_TX_CTL1); +} + +static void sun8i_dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan) +{ + u32 v; + + v = readl(ioaddr + EMAC_TX_CTL1); + v &= ~EMAC_TX_DMA_EN; + writel(v, ioaddr + EMAC_TX_CTL1); +} + +static void sun8i_dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan) +{ + u32 v; + + v = readl(ioaddr + EMAC_RX_CTL1); + v |= EMAC_RX_DMA_START; + v |= EMAC_RX_DMA_EN; + writel(v, ioaddr + EMAC_RX_CTL1); +} + +static void sun8i_dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan) +{ + u32 v; + + v = readl(ioaddr + EMAC_RX_CTL1); + v &= ~EMAC_RX_DMA_EN; + writel(v, ioaddr + EMAC_RX_CTL1); +} + +static int sun8i_dwmac_dma_interrupt(void __iomem *ioaddr, + struct stmmac_extra_stats *x, u32 chan) +{ + u32 v; + int ret = 0; + + v = readl(ioaddr + EMAC_INT_STA); + + if (v & EMAC_TX_INT) { + ret |= handle_tx; + x->tx_normal_irq_n++; + } + + if (v & EMAC_TX_DMA_STOP_INT) + x->tx_process_stopped_irq++; + + if (v & EMAC_TX_BUF_UA_INT) + x->tx_process_stopped_irq++; + + if (v & EMAC_TX_TIMEOUT_INT) + ret |= tx_hard_error; + + if (v & EMAC_TX_UNDERFLOW_INT) { + ret |= tx_hard_error; + x->tx_undeflow_irq++; + } + + if (v & EMAC_TX_EARLY_INT) + x->tx_early_irq++; + + if (v & EMAC_RX_INT) { + ret |= handle_rx; + x->rx_normal_irq_n++; + } + + if (v & EMAC_RX_BUF_UA_INT) + x->rx_buf_unav_irq++; + + if (v & EMAC_RX_DMA_STOP_INT) + x->rx_process_stopped_irq++; + + if (v & EMAC_RX_TIMEOUT_INT) + ret |= tx_hard_error; + + if (v & EMAC_RX_OVERFLOW_INT) { + ret |= tx_hard_error; + x->rx_overflow_irq++; + } + + if (v & EMAC_RX_EARLY_INT) + x->rx_early_irq++; + + if (v & EMAC_RGMII_STA_INT) + x->irq_rgmii_n++; + + writel(v, ioaddr + EMAC_INT_STA); + + return ret; +} + +static void sun8i_dwmac_dma_operation_mode(void __iomem *ioaddr, int txmode, + int rxmode, int rxfifosz) +{ + u32 v; + + v = readl(ioaddr + EMAC_TX_CTL1); + if (txmode == SF_DMA_MODE) { + v |= EMAC_TX_MD; + /* Undocumented bit (called TX_NEXT_FRM in BSP), the original + * comment is + * "Operating on second frame increase the performance + * especially when transmit store-and-forward is used." + */ + v |= EMAC_TX_NEXT_FRM; + } else { + v &= ~EMAC_TX_MD; + v &= ~EMAC_TX_TH_MASK; + if (txmode < 64) + v |= EMAC_TX_TH_64; + else if (txmode < 128) + v |= EMAC_TX_TH_128; + else if (txmode < 192) + v |= EMAC_TX_TH_192; + else if (txmode < 256) + v |= EMAC_TX_TH_256; + } + writel(v, ioaddr + EMAC_TX_CTL1); + + v = readl(ioaddr + EMAC_RX_CTL1); + if (rxmode == SF_DMA_MODE) { + v |= EMAC_RX_MD; + } else { + v &= ~EMAC_RX_MD; + v &= ~EMAC_RX_TH_MASK; + if (rxmode < 32) + v |= EMAC_RX_TH_32; + else if (rxmode < 64) + v |= EMAC_RX_TH_64; + else if (rxmode < 96) + v |= EMAC_RX_TH_96; + else if (rxmode < 128) + v |= EMAC_RX_TH_128; + } + writel(v, ioaddr + EMAC_RX_CTL1); +} + +static const struct stmmac_dma_ops sun8i_dwmac_dma_ops = { + .reset = sun8i_dwmac_dma_reset, + .init = sun8i_dwmac_dma_init, + .dump_regs = sun8i_dwmac_dump_regs, + .dma_mode = sun8i_dwmac_dma_operation_mode, + .enable_dma_transmission = sun8i_dwmac_enable_dma_transmission, + .enable_dma_irq = sun8i_dwmac_enable_dma_irq, + .disable_dma_irq = sun8i_dwmac_disable_dma_irq, + .start_tx = sun8i_dwmac_dma_start_tx, + .stop_tx = sun8i_dwmac_dma_stop_tx, + .start_rx = sun8i_dwmac_dma_start_rx, + .stop_rx = sun8i_dwmac_dma_stop_rx, + .dma_interrupt = sun8i_dwmac_dma_interrupt, +}; + +static int sun8i_dwmac_init(struct platform_device *pdev, void *priv) +{ + struct sunxi_priv_data *gmac = priv; + int ret; + + if (gmac->regulator) { + ret = regulator_enable(gmac->regulator); + if (ret) { + dev_err(&pdev->dev, "Fail to enable regulator\n"); + return ret; + } + } + + ret = clk_prepare_enable(gmac->tx_clk); + if (ret) { + if (gmac->regulator) + regulator_disable(gmac->regulator); + dev_err(&pdev->dev, "Could not enable AHB clock\n"); + return ret; + } + + return 0; +} + +static void sun8i_dwmac_core_init(struct mac_device_info *hw, int mtu) +{ + void __iomem *ioaddr = hw->pcsr; + u32 v; + + v = (8 << EMAC_BURSTLEN_SHIFT); /* burst len */ + writel(v, ioaddr + EMAC_BASIC_CTL1); +} + +static void sun8i_dwmac_set_mac(void __iomem *ioaddr, bool enable) +{ + u32 t, r; + + t = readl(ioaddr + EMAC_TX_CTL0); + r = readl(ioaddr + EMAC_RX_CTL0); + if (enable) { + t |= EMAC_TX_TRANSMITTER_EN; + r |= EMAC_RX_RECEIVER_EN; + } else { + t &= ~EMAC_TX_TRANSMITTER_EN; + r &= ~EMAC_RX_RECEIVER_EN; + } + writel(t, ioaddr + EMAC_TX_CTL0); + writel(r, ioaddr + EMAC_RX_CTL0); +} + +/* Set MAC address at slot reg_n + * All slot > 0 need to be enabled with MAC_ADDR_TYPE_DST + * If addr is NULL, clear the slot + */ +static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw, + unsigned char *addr, + unsigned int reg_n) +{ + void __iomem *ioaddr = hw->pcsr; + u32 v; + + if (!addr) { + writel(0, ioaddr + EMAC_MACADDR_HI(reg_n)); + return; + } + + stmmac_set_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n), + EMAC_MACADDR_LO(reg_n)); + if (reg_n > 0) { + v = readl(ioaddr + EMAC_MACADDR_HI(reg_n)); + v |= MAC_ADDR_TYPE_DST; + writel(v, ioaddr + EMAC_MACADDR_HI(reg_n)); + } +} + +static void sun8i_dwmac_get_umac_addr(struct mac_device_info *hw, + unsigned char *addr, + unsigned int reg_n) +{ + void __iomem *ioaddr = hw->pcsr; + + stmmac_get_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n), + EMAC_MACADDR_LO(reg_n)); +} + +/* caution this function must return non 0 to work */ +static int sun8i_dwmac_rx_ipc_enable(struct mac_device_info *hw) +{ + void __iomem *ioaddr = hw->pcsr; + u32 v; + + v = readl(ioaddr + EMAC_RX_CTL0); + v |= EMAC_RX_DO_CRC; + writel(v, ioaddr + EMAC_RX_CTL0); + + return 1; +} + +static void sun8i_dwmac_set_filter(struct mac_device_info *hw, + struct net_device *dev) +{ + void __iomem *ioaddr = hw->pcsr; + u32 v; + int i = 1; + struct netdev_hw_addr *ha; + int macaddrs = netdev_uc_count(dev) + netdev_mc_count(dev) + 1; + + v = EMAC_FRM_FLT_CTL; + + if (dev->flags & IFF_PROMISC) { + v = EMAC_FRM_FLT_RXALL; + } else if (dev->flags & IFF_ALLMULTI) { + v |= EMAC_FRM_FLT_MULTICAST; + } else if (macaddrs <= hw->unicast_filter_entries) { + if (!netdev_mc_empty(dev)) { + netdev_for_each_mc_addr(ha, dev) { + sun8i_dwmac_set_umac_addr(hw, ha->addr, i); + i++; + } + } + if (!netdev_uc_empty(dev)) { + netdev_for_each_uc_addr(ha, dev) { + sun8i_dwmac_set_umac_addr(hw, ha->addr, i); + i++; + } + } + } else { + netdev_info(dev, "Too many address, switching to promiscuous\n"); + v = EMAC_FRM_FLT_RXALL; + } + + /* Disable unused address filter slots */ + while (i < hw->unicast_filter_entries) + sun8i_dwmac_set_umac_addr(hw, NULL, i++); + + writel(v, ioaddr + EMAC_RX_FRM_FLT); +} + +static void sun8i_dwmac_flow_ctrl(struct mac_device_info *hw, + unsigned int duplex, unsigned int fc, + unsigned int pause_time, u32 tx_cnt) +{ + void __iomem *ioaddr = hw->pcsr; + u32 v; + + v = readl(ioaddr + EMAC_RX_CTL0); + if (fc == FLOW_AUTO) + v |= EMAC_RX_FLOW_CTL_EN; + else + v &= ~EMAC_RX_FLOW_CTL_EN; + writel(v, ioaddr + EMAC_RX_CTL0); + + v = readl(ioaddr + EMAC_TX_FLOW_CTL); + if (fc == FLOW_AUTO) + v |= EMAC_TX_FLOW_CTL_EN; + else + v &= ~EMAC_TX_FLOW_CTL_EN; + writel(v, ioaddr + EMAC_TX_FLOW_CTL); +} + +static int sun8i_dwmac_reset(struct stmmac_priv *priv) +{ + u32 v; + int err; + + v = readl(priv->ioaddr + EMAC_BASIC_CTL1); + writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1); + + /* The timeout was previoulsy set to 10ms, but some board (OrangePI0) + * need more if no cable plugged. 100ms seems OK + */ + err = readl_poll_timeout(priv->ioaddr + EMAC_BASIC_CTL1, v, + !(v & 0x01), 100, 100000); + + if (err) { + dev_err(priv->device, "EMAC reset timeout\n"); + return -EFAULT; + } + return 0; +} + +static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv) +{ + struct sunxi_priv_data *gmac = priv->plat->bsp_priv; + struct device_node *node = priv->device->of_node; + int ret; + u32 reg, val; + + regmap_read(gmac->regmap, SYSCON_EMAC_REG, &val); + reg = gmac->variant->default_syscon_value; + if (reg != val) + dev_warn(priv->device, + "Current syscon value is not the default %x (expect %x)\n", + val, reg); + + if (gmac->variant->internal_phy) { + if (!gmac->use_internal_phy) { + /* switch to external PHY interface */ + reg &= ~H3_EPHY_SELECT; + } else { + reg |= H3_EPHY_SELECT; + reg &= ~H3_EPHY_SHUTDOWN; + dev_dbg(priv->device, "Select internal_phy %x\n", reg); + + if (of_property_read_bool(priv->plat->phy_node, + "allwinner,leds-active-low")) + reg |= H3_EPHY_LED_POL; + else + reg &= ~H3_EPHY_LED_POL; + + ret = of_mdio_parse_addr(priv->device, + priv->plat->phy_node); + if (ret < 0) { + dev_err(priv->device, "Could not parse MDIO addr\n"); + return ret; + } + /* of_mdio_parse_addr returns a valid (0 ~ 31) PHY + * address. No need to mask it again. + */ + reg |= ret << H3_EPHY_ADDR_SHIFT; + } + } + + if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) { + if (val % 100) { + dev_err(priv->device, "tx-delay must be a multiple of 100\n"); + return -EINVAL; + } + val /= 100; + dev_dbg(priv->device, "set tx-delay to %x\n", val); + if (val <= SYSCON_ETXDC_MASK) { + reg &= ~(SYSCON_ETXDC_MASK << SYSCON_ETXDC_SHIFT); + reg |= (val << SYSCON_ETXDC_SHIFT); + } else { + dev_err(priv->device, "Invalid TX clock delay: %d\n", + val); + return -EINVAL; + } + } + + if (!of_property_read_u32(node, "allwinner,rx-delay-ps", &val)) { + if (val % 100) { + dev_err(priv->device, "rx-delay must be a multiple of 100\n"); + return -EINVAL; + } + val /= 100; + dev_dbg(priv->device, "set rx-delay to %x\n", val); + if (val <= SYSCON_ERXDC_MASK) { + reg &= ~(SYSCON_ERXDC_MASK << SYSCON_ERXDC_SHIFT); + reg |= (val << SYSCON_ERXDC_SHIFT); + } else { + dev_err(priv->device, "Invalid RX clock delay: %d\n", + val); + return -EINVAL; + } + } + + /* Clear interface mode bits */ + reg &= ~(SYSCON_ETCS_MASK | SYSCON_EPIT); + if (gmac->variant->support_rmii) + reg &= ~SYSCON_RMII_EN; + + switch (priv->plat->interface) { + case PHY_INTERFACE_MODE_MII: + /* default */ + break; + case PHY_INTERFACE_MODE_RGMII: + reg |= SYSCON_EPIT | SYSCON_ETCS_INT_GMII; + break; + case PHY_INTERFACE_MODE_RMII: + reg |= SYSCON_RMII_EN | SYSCON_ETCS_EXT_GMII; + break; + default: + dev_err(priv->device, "Unsupported interface mode: %s", + phy_modes(priv->plat->interface)); + return -EINVAL; + } + + regmap_write(gmac->regmap, SYSCON_EMAC_REG, reg); + + return 0; +} + +static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac) +{ + u32 reg = gmac->variant->default_syscon_value; + + regmap_write(gmac->regmap, SYSCON_EMAC_REG, reg); +} + +static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv) +{ + struct sunxi_priv_data *gmac = priv->plat->bsp_priv; + int ret; + + if (!gmac->use_internal_phy) + return 0; + + ret = clk_prepare_enable(gmac->ephy_clk); + if (ret) { + dev_err(priv->device, "Cannot enable ephy\n"); + return ret; + } + + ret = reset_control_deassert(gmac->rst_ephy); + if (ret) { + dev_err(priv->device, "Cannot deassert ephy\n"); + clk_disable_unprepare(gmac->ephy_clk); + return ret; + } + + return 0; +} + +static int sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac) +{ + if (!gmac->use_internal_phy) + return 0; + + clk_disable_unprepare(gmac->ephy_clk); + reset_control_assert(gmac->rst_ephy); + return 0; +} + +/* sun8i_power_phy() - Activate the PHY: + * In case of error, no need to call sun8i_unpower_phy(), + * it will be called anyway by sun8i_dwmac_exit() + */ +static int sun8i_power_phy(struct stmmac_priv *priv) +{ + int ret; + + ret = sun8i_dwmac_power_internal_phy(priv); + if (ret) + return ret; + + ret = sun8i_dwmac_set_syscon(priv); + if (ret) + return ret; + + /* After changing syscon value, the MAC need reset or it will use + * the last value (and so the last PHY set. + */ + ret = sun8i_dwmac_reset(priv); + if (ret) + return ret; + return 0; +} + +static void sun8i_unpower_phy(struct sunxi_priv_data *gmac) +{ + sun8i_dwmac_unset_syscon(gmac); + sun8i_dwmac_unpower_internal_phy(gmac); +} + +static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv) +{ + struct sunxi_priv_data *gmac = priv; + + sun8i_unpower_phy(gmac); + + clk_disable_unprepare(gmac->tx_clk); + + if (gmac->regulator) + regulator_disable(gmac->regulator); +} + +static const struct stmmac_ops sun8i_dwmac_ops = { + .core_init = sun8i_dwmac_core_init, + .set_mac = sun8i_dwmac_set_mac, + .dump_regs = sun8i_dwmac_dump_mac_regs, + .rx_ipc = sun8i_dwmac_rx_ipc_enable, + .set_filter = sun8i_dwmac_set_filter, + .flow_ctrl = sun8i_dwmac_flow_ctrl, + .set_umac_addr = sun8i_dwmac_set_umac_addr, + .get_umac_addr = sun8i_dwmac_get_umac_addr, +}; + +static struct mac_device_info *sun8i_dwmac_setup(void *ppriv) +{ + struct mac_device_info *mac; + struct stmmac_priv *priv = ppriv; + int ret; + + mac = devm_kzalloc(priv->device, sizeof(*mac), GFP_KERNEL); + if (!mac) + return NULL; + + ret = sun8i_power_phy(priv); + if (ret) + return NULL; + + mac->pcsr = priv->ioaddr; + mac->mac = &sun8i_dwmac_ops; + mac->dma = &sun8i_dwmac_dma_ops; + + /* The loopback bit seems to be re-set when link change + * Simply mask it each time + * Speed 10/100/1000 are set in BIT(2)/BIT(3) + */ + mac->link.speed_mask = GENMASK(3, 2) | EMAC_LOOPBACK; + mac->link.speed10 = EMAC_SPEED_10; + mac->link.speed100 = EMAC_SPEED_100; + mac->link.speed1000 = EMAC_SPEED_1000; + mac->link.duplex = EMAC_DUPLEX_FULL; + mac->mii.addr = EMAC_MDIO_CMD; + mac->mii.data = EMAC_MDIO_DATA; + mac->mii.reg_shift = 4; + mac->mii.reg_mask = GENMASK(8, 4); + mac->mii.addr_shift = 12; + mac->mii.addr_mask = GENMASK(16, 12); + mac->mii.clk_csr_shift = 20; + mac->mii.clk_csr_mask = GENMASK(22, 20); + mac->unicast_filter_entries = 8; + + /* Synopsys Id is not available */ + priv->synopsys_id = 0; + + return mac; +} + +static int sun8i_dwmac_probe(struct platform_device *pdev) +{ + struct plat_stmmacenet_data *plat_dat; + struct stmmac_resources stmmac_res; + struct sunxi_priv_data *gmac; + struct device *dev = &pdev->dev; + int ret; + + ret = stmmac_get_platform_resources(pdev, &stmmac_res); + if (ret) + return ret; + + plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); + if (IS_ERR(plat_dat)) + return PTR_ERR(plat_dat); + + gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL); + if (!gmac) + return -ENOMEM; + + gmac->variant = of_device_get_match_data(&pdev->dev); + if (!gmac->variant) { + dev_err(&pdev->dev, "Missing dwmac-sun8i variant\n"); + return -EINVAL; + } + + gmac->tx_clk = devm_clk_get(dev, "stmmaceth"); + if (IS_ERR(gmac->tx_clk)) { + dev_err(dev, "Could not get TX clock\n"); + return PTR_ERR(gmac->tx_clk); + } + + /* Optional regulator for PHY */ + gmac->regulator = devm_regulator_get_optional(dev, "phy"); + if (IS_ERR(gmac->regulator)) { + if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER) + return -EPROBE_DEFER; + dev_info(dev, "No regulator found\n"); + gmac->regulator = NULL; + } + + gmac->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, + "syscon"); + if (IS_ERR(gmac->regmap)) { + ret = PTR_ERR(gmac->regmap); + dev_err(&pdev->dev, "Unable to map syscon: %d\n", ret); + return ret; + } + + plat_dat->interface = of_get_phy_mode(dev->of_node); + if (plat_dat->interface == gmac->variant->internal_phy) { + dev_info(&pdev->dev, "Will use internal PHY\n"); + gmac->use_internal_phy = true; + gmac->ephy_clk = of_clk_get(plat_dat->phy_node, 0); + if (IS_ERR(gmac->ephy_clk)) { + ret = PTR_ERR(gmac->ephy_clk); + dev_err(&pdev->dev, "Cannot get EPHY clock: %d\n", ret); + return -EINVAL; + } + + gmac->rst_ephy = of_reset_control_get(plat_dat->phy_node, NULL); + if (IS_ERR(gmac->rst_ephy)) { + ret = PTR_ERR(gmac->rst_ephy); + if (ret == -EPROBE_DEFER) + return ret; + dev_err(&pdev->dev, "No EPHY reset control found %d\n", + ret); + return -EINVAL; + } + } else { + dev_info(&pdev->dev, "Will use external PHY\n"); + gmac->use_internal_phy = false; + } + + /* platform data specifying hardware features and callbacks. + * hardware features were copied from Allwinner drivers. + */ + plat_dat->rx_coe = STMMAC_RX_COE_TYPE2; + plat_dat->tx_coe = 1; + plat_dat->has_sun8i = true; + plat_dat->bsp_priv = gmac; + plat_dat->init = sun8i_dwmac_init; + plat_dat->exit = sun8i_dwmac_exit; + plat_dat->setup = sun8i_dwmac_setup; + + ret = sun8i_dwmac_init(pdev, plat_dat->bsp_priv); + if (ret) + return ret; + + ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); + if (ret) + sun8i_dwmac_exit(pdev, plat_dat->bsp_priv); + + return ret; +} + +static const struct of_device_id sun8i_dwmac_match[] = { + { .compatible = "allwinner,sun8i-h3-emac", + .data = &emac_variant_h3 }, + { .compatible = "allwinner,sun8i-a83t-emac", + .data = &emac_variant_a83t }, + { .compatible = "allwinner,sun50i-a64-emac", + .data = &emac_variant_a64 }, + { } +}; +MODULE_DEVICE_TABLE(of, sun8i_dwmac_match); + +static struct platform_driver sun8i_dwmac_driver = { + .probe = sun8i_dwmac_probe, + .remove = stmmac_pltfr_remove, + .driver = { + .name = "dwmac-sun8i", + .pm = &stmmac_pltfr_pm_ops, + .of_match_table = sun8i_dwmac_match, + }, +}; +module_platform_driver(sun8i_dwmac_driver); + +MODULE_AUTHOR("Corentin Labbe <clabbe.montjoie@gmail.com>"); +MODULE_DESCRIPTION("Allwinner sun8i DWMAC specific glue layer"); +MODULE_LICENSE("GPL"); diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index c80c9c3b67db..68a188e74c54 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -235,6 +235,17 @@ static void stmmac_clk_csr_set(struct stmmac_priv *priv) else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) priv->clk_csr = STMMAC_CSR_250_300M; } + + if (priv->plat->has_sun8i) { + if (clk_rate > 160000000) + priv->clk_csr = 0x03; + else if (clk_rate > 80000000) + priv->clk_csr = 0x02; + else if (clk_rate > 40000000) + priv->clk_csr = 0x01; + else + priv->clk_csr = 0; + } } static void print_pkt(unsigned char *buf, int len) @@ -3955,6 +3966,10 @@ static int stmmac_hw_init(struct stmmac_priv *priv) priv->hw = mac; + /* dwmac-sun8i only work in chain mode */ + if (priv->plat->has_sun8i) + chain_mode = 1; + /* To use the chained or ring mode */ if (priv->synopsys_id >= DWMAC_CORE_4_00) { priv->hw->mode = &dwmac4_ring_mode_ops; diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c index 7fc3a1ef395a..3840529344ed 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c @@ -309,6 +309,12 @@ static int stmmac_dt_phy(struct plat_stmmacenet_data *plat, struct device_node *np, struct device *dev) { bool mdio = true; + static const struct of_device_id need_mdio_ids[] = { + { .compatible = "snps,dwc-qos-ethernet-4.10" }, + { .compatible = "allwinner,sun8i-a83t-emac" }, + { .compatible = "allwinner,sun8i-h3-emac" }, + { .compatible = "allwinner,sun50i-a64-emac" }, + }; /* If phy-handle property is passed from DT, use it as the PHY */ plat->phy_node = of_parse_phandle(np, "phy-handle", 0); @@ -325,8 +331,7 @@ static int stmmac_dt_phy(struct plat_stmmacenet_data *plat, mdio = false; } - /* exception for dwmac-dwc-qos-eth glue logic */ - if (of_device_is_compatible(np, "snps,dwc-qos-ethernet-4.10")) { + if (of_match_node(need_mdio_ids, np)) { plat->mdio_node = of_get_child_by_name(np, "mdio"); } else { /** diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index 8bb550bca96d..108739ff9223 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -186,6 +186,7 @@ struct plat_stmmacenet_data { struct reset_control *stmmac_rst; struct stmmac_axi *axi; int has_gmac4; + bool has_sun8i; bool tso_en; int mac_port_sel_speed; bool en_tx_lpi_clockgating;
The dwmac-sun8i is a heavy hacked version of stmmac hardware by allwinner. In fact the only common part is the descriptor management and the first register function. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> --- drivers/net/ethernet/stmicro/stmmac/Kconfig | 11 + drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 990 +++++++++++++++++++++ drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 15 + .../net/ethernet/stmicro/stmmac/stmmac_platform.c | 9 +- include/linux/stmmac.h | 1 + 6 files changed, 1025 insertions(+), 2 deletions(-) create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c