diff mbox

[11/13] drm/i915/bxt: Enable IPC support

Message ID 20170713103902.11668-1-mahesh1.kumar@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Kumar, Mahesh July 13, 2017, 10:39 a.m. UTC 
From: "Kumar, Mahesh" <mahesh1.kumar@intel.com>

This patch adds IPC support. This patch also enables IPC in all supported
platforms.
IPC (Isochronous Priority Control) is the hardware feature, which
dynamically controls the memory read priority of Display.

When IPC is enabled, plane read requests are sent at high priority until
filling above the transition watermark, then the requests are sent at
lower priority until dropping below the level 0 watermark.
The lower priority requests allow other memory clients to have better
memory access. When IPC is disabled, all plane read requests are sent at
high priority.

Changes since V1:
 - Remove commandline parameter to disable ipc
 - Address Paulo's comments
Changes since V2:
 - Address review comments
 - Set ipc_enabled flag
Changes since V3:
 - move ipc_enabled flag assignment inside intel_ipc_enable function
Changes since V4:
 - Re-enable IPC after suspend/resume
Changes since V5:
 - Enable IPC for all gen >=9 except SKL
Changes since V6:
 - fix commit msg
 - after resume program IPC based on SW state.

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c      |  4 +++-
 drivers/gpu/drm/i915/i915_reg.h      |  1 +
 drivers/gpu/drm/i915/intel_display.c |  1 +
 drivers/gpu/drm/i915/intel_drv.h     |  2 ++
 drivers/gpu/drm/i915/intel_pm.c      | 24 ++++++++++++++++++++++++
 5 files changed, 31 insertions(+), 1 deletion(-)

Comments

Chris Wilson July 13, 2017, 10:48 a.m. UTC | #1 
Quoting Mahesh Kumar (2017-07-13 11:39:02)
> +void intel_enable_ipc(struct drm_i915_private *dev_priv)
> +{
> +       u32 val;
> +
> +       val = I915_READ(DISP_ARB_CTL2);
> +
> +       if (dev_priv->ipc_enabled)
> +               val |= DISP_IPC_ENABLE;
> +       else
> +               val &= ~DISP_IPC_ENABLE;
> +
> +       I915_WRITE(DISP_ARB_CTL2, val);
> +}
> +
> +void intel_init_ipc(struct drm_i915_private *dev_priv)
> +{
> +       dev_priv->ipc_enabled = false;
> +       if (INTEL_GEN(dev_priv) < 9 || IS_SKYLAKE(dev_priv))
> +               return;

So dev_priv->ipc_enabled is just a dev_priv->info.has_ipc, its state
never changes at runtime? Using a intel_device_info field then has a few
useful side-effects including automatic printing in the lists of
capabilities.
-Chris
Kumar, Mahesh July 13, 2017, 12:02 p.m. UTC | #2 
Hi,


On Thursday 13 July 2017 04:18 PM, Chris Wilson wrote:
> Quoting Mahesh Kumar (2017-07-13 11:39:02)
>> +void intel_enable_ipc(struct drm_i915_private *dev_priv)
>> +{
>> +       u32 val;
>> +
>> +       val = I915_READ(DISP_ARB_CTL2);
>> +
>> +       if (dev_priv->ipc_enabled)
>> +               val |= DISP_IPC_ENABLE;
>> +       else
>> +               val &= ~DISP_IPC_ENABLE;
>> +
>> +       I915_WRITE(DISP_ARB_CTL2, val);
>> +}
>> +
>> +void intel_init_ipc(struct drm_i915_private *dev_priv)
>> +{
>> +       dev_priv->ipc_enabled = false;
>> +       if (INTEL_GEN(dev_priv) < 9 || IS_SKYLAKE(dev_priv))
>> +               return;
> So dev_priv->ipc_enabled is just a dev_priv->info.has_ipc, its state
> never changes at runtime?
For debug purpose we may want to disable ipc, So no, it's value 
(dev_priv->ipc_enabled) will not be a fixed value.
I have a plan to make a debugfs entry to change the IPC value at runtime.
But having it also in dev_priv->info.has_ipc a good idea, It will make 
condition check easy.
I'll float another patch incorporating this change.

thanks,
-Mahesh
> Using a intel_device_info field then has a few
> useful side-effects including automatic printing in the lists of
> capabilities.
> -Chris
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9167a73f3c69..340424ed1fce 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1334,7 +1334,7 @@  int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
 
 	intel_runtime_pm_enable(dev_priv);
 
-	dev_priv->ipc_enabled = false;
+	intel_init_ipc(dev_priv);
 
 	if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
 		DRM_INFO("DRM_I915_DEBUG enabled\n");
@@ -2598,6 +2598,8 @@  static int intel_runtime_resume(struct device *kdev)
 	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
 		intel_hpd_init(dev_priv);
 
+	intel_enable_ipc(dev_priv);
+
 	enable_rpm_wakeref_asserts(dev_priv);
 
 	if (ret)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 64cc674b652a..09af90f8cd0a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6728,6 +6728,7 @@  enum {
 #define  DISP_FBC_WM_DIS		(1<<15)
 #define DISP_ARB_CTL2	_MMIO(0x45004)
 #define  DISP_DATA_PARTITION_5_6	(1<<6)
+#define  DISP_IPC_ENABLE		(1<<3)
 #define DBUF_CTL	_MMIO(0x45008)
 #define  DBUF_POWER_REQUEST		(1<<31)
 #define  DBUF_POWER_STATE		(1<<30)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0648fd74be87..e610b4395dcc 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15723,6 +15723,7 @@  void intel_display_resume(struct drm_device *dev)
 	if (!ret)
 		ret = __intel_display_resume(dev, state, &ctx);
 
+	intel_enable_ipc(dev_priv);
 	drm_modeset_drop_locks(&ctx);
 	drm_modeset_acquire_fini(&ctx);
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d17a32437f07..9f52922afce6 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1883,6 +1883,8 @@  bool ilk_disable_lp_wm(struct drm_device *dev);
 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
 				  struct intel_crtc_state *cstate);
+void intel_init_ipc(struct drm_i915_private *dev_priv);
+void intel_enable_ipc(struct drm_i915_private *dev_priv);
 static inline int intel_enable_rc6(void)
 {
 	return i915.enable_rc6;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ad3b3d758d5c..e2641ddeb2bf 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5772,6 +5772,30 @@  void intel_update_watermarks(struct intel_crtc *crtc)
 		dev_priv->display.update_wm(crtc);
 }
 
+void intel_enable_ipc(struct drm_i915_private *dev_priv)
+{
+	u32 val;
+
+	val = I915_READ(DISP_ARB_CTL2);
+
+	if (dev_priv->ipc_enabled)
+		val |= DISP_IPC_ENABLE;
+	else
+		val &= ~DISP_IPC_ENABLE;
+
+	I915_WRITE(DISP_ARB_CTL2, val);
+}
+
+void intel_init_ipc(struct drm_i915_private *dev_priv)
+{
+	dev_priv->ipc_enabled = false;
+	if (INTEL_GEN(dev_priv) < 9 || IS_SKYLAKE(dev_priv))
+		return;
+
+	dev_priv->ipc_enabled = true;
+	intel_enable_ipc(dev_priv);
+}
+
 /*
  * Lock protecting IPS related data structures
  */