| Message ID | 20170714064302.20383-5-wens@csie.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
On 14 July 2017 at 08:42, Chen-Yu Tsai <wens@csie.org> wrote: > The register for the "new timing mode" also has bit fields for setting > output and sample timing phases. According to comments in Allwinner's > BSP kernel, the default values are good enough. > > Keep the default values already in the hardware when setting new timing > mode, instead of overwriting the whole register. > > Fixes: 9a37e53e451e ("mmc: sunxi: Enable the new timings for the A64 MMC > controllers") > Signed-off-by: Chen-Yu Tsai <wens@csie.org> It looks like this change doesn't depend on anything else? Do you want me to pick it up for fixes and adding stable tag? Kind regards Uffe > --- > drivers/mmc/host/sunxi-mmc.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c > index d6fa2214aaae..0fb4e4c119e1 100644 > --- a/drivers/mmc/host/sunxi-mmc.c > +++ b/drivers/mmc/host/sunxi-mmc.c > @@ -793,8 +793,12 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host, > } > mmc_writel(host, REG_CLKCR, rval); > > - if (host->cfg->needs_new_timings) > - mmc_writel(host, REG_SD_NTSR, SDXC_2X_TIMING_MODE); > + if (host->cfg->needs_new_timings) { > + /* Don't touch the delay bits */ > + rval = mmc_readl(host, REG_SD_NTSR); > + rval |= SDXC_2X_TIMING_MODE; > + mmc_writel(host, REG_SD_NTSR, rval); > + } > > ret = sunxi_mmc_clk_set_phase(host, ios, rate); > if (ret) > -- > 2.13.2 > -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Fri, Jul 14, 2017 at 5:16 PM, Ulf Hansson <ulf.hansson@linaro.org> wrote: > On 14 July 2017 at 08:42, Chen-Yu Tsai <wens@csie.org> wrote: >> The register for the "new timing mode" also has bit fields for setting >> output and sample timing phases. According to comments in Allwinner's >> BSP kernel, the default values are good enough. >> >> Keep the default values already in the hardware when setting new timing >> mode, instead of overwriting the whole register. >> >> Fixes: 9a37e53e451e ("mmc: sunxi: Enable the new timings for the A64 MMC >> controllers") >> Signed-off-by: Chen-Yu Tsai <wens@csie.org> > > It looks like this change doesn't depend on anything else? Do you want > me to pick it up for fixes and adding stable tag? Yes, please. ChenYu > > Kind regards > Uffe > >> --- >> drivers/mmc/host/sunxi-mmc.c | 8 ++++++-- >> 1 file changed, 6 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c >> index d6fa2214aaae..0fb4e4c119e1 100644 >> --- a/drivers/mmc/host/sunxi-mmc.c >> +++ b/drivers/mmc/host/sunxi-mmc.c >> @@ -793,8 +793,12 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host, >> } >> mmc_writel(host, REG_CLKCR, rval); >> >> - if (host->cfg->needs_new_timings) >> - mmc_writel(host, REG_SD_NTSR, SDXC_2X_TIMING_MODE); >> + if (host->cfg->needs_new_timings) { >> + /* Don't touch the delay bits */ >> + rval = mmc_readl(host, REG_SD_NTSR); >> + rval |= SDXC_2X_TIMING_MODE; >> + mmc_writel(host, REG_SD_NTSR, rval); >> + } >> >> ret = sunxi_mmc_clk_set_phase(host, ios, rate); >> if (ret) >> -- >> 2.13.2 >> -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Fri, Jul 14, 2017 at 02:42:55PM +0800, Chen-Yu Tsai wrote: > The register for the "new timing mode" also has bit fields for setting > output and sample timing phases. According to comments in Allwinner's > BSP kernel, the default values are good enough. > > Keep the default values already in the hardware when setting new timing > mode, instead of overwriting the whole register. > > Fixes: 9a37e53e451e ("mmc: sunxi: Enable the new timings for the A64 MMC > controllers") > Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Thanks! Maxime
+stable On 14 July 2017 at 08:42, Chen-Yu Tsai <wens@csie.org> wrote: > The register for the "new timing mode" also has bit fields for setting > output and sample timing phases. According to comments in Allwinner's > BSP kernel, the default values are good enough. > > Keep the default values already in the hardware when setting new timing > mode, instead of overwriting the whole register. > > Fixes: 9a37e53e451e ("mmc: sunxi: Enable the new timings for the A64 MMC > controllers") > Signed-off-by: Chen-Yu Tsai <wens@csie.org> Thanks, applied for fixes and added a stable tag. Kind regards Uffe > --- > drivers/mmc/host/sunxi-mmc.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c > index d6fa2214aaae..0fb4e4c119e1 100644 > --- a/drivers/mmc/host/sunxi-mmc.c > +++ b/drivers/mmc/host/sunxi-mmc.c > @@ -793,8 +793,12 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host, > } > mmc_writel(host, REG_CLKCR, rval); > > - if (host->cfg->needs_new_timings) > - mmc_writel(host, REG_SD_NTSR, SDXC_2X_TIMING_MODE); > + if (host->cfg->needs_new_timings) { > + /* Don't touch the delay bits */ > + rval = mmc_readl(host, REG_SD_NTSR); > + rval |= SDXC_2X_TIMING_MODE; > + mmc_writel(host, REG_SD_NTSR, rval); > + } > > ret = sunxi_mmc_clk_set_phase(host, ios, rate); > if (ret) > -- > 2.13.2 > -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c index d6fa2214aaae..0fb4e4c119e1 100644 --- a/drivers/mmc/host/sunxi-mmc.c +++ b/drivers/mmc/host/sunxi-mmc.c @@ -793,8 +793,12 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host, } mmc_writel(host, REG_CLKCR, rval); - if (host->cfg->needs_new_timings) - mmc_writel(host, REG_SD_NTSR, SDXC_2X_TIMING_MODE); + if (host->cfg->needs_new_timings) { + /* Don't touch the delay bits */ + rval = mmc_readl(host, REG_SD_NTSR); + rval |= SDXC_2X_TIMING_MODE; + mmc_writel(host, REG_SD_NTSR, rval); + } ret = sunxi_mmc_clk_set_phase(host, ios, rate); if (ret)
The register for the "new timing mode" also has bit fields for setting output and sample timing phases. According to comments in Allwinner's BSP kernel, the default values are good enough. Keep the default values already in the hardware when setting new timing mode, instead of overwriting the whole register. Fixes: 9a37e53e451e ("mmc: sunxi: Enable the new timings for the A64 MMC controllers") Signed-off-by: Chen-Yu Tsai <wens@csie.org> --- drivers/mmc/host/sunxi-mmc.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)