| Message ID | 20170623164544.7362-5-ben@bwidawsk.net (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Jun 23, 2017 at 09:45:44AM -0700, Ben Widawsky wrote: > v2: > Support sprite plane. > Support pipe C/D limitation on GEN9. > > This requires rebase on the correct Ville patches > > Cc: Daniel Stone <daniels@collabora.com> > Cc: Kristian Høgsberg <krh@bitplanet.net> > Signed-off-by: Ben Widawsky <ben@bwidawsk.net> > --- > drivers/gpu/drm/i915/intel_display.c | 34 +++++++++++++++++++++++++------ > drivers/gpu/drm/i915/intel_sprite.c | 39 +++++++++++++++++++++++++++++++++++- > 2 files changed, 66 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 877a51514c61..2a0e5cd26059 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -93,7 +93,17 @@ static const uint32_t skl_primary_formats[] = { > DRM_FORMAT_VYUY, > }; > > +static const uint64_t skl_format_modifiers_noccs[] = { > + I915_FORMAT_MOD_Yf_TILED, > + I915_FORMAT_MOD_Y_TILED, > + I915_FORMAT_MOD_X_TILED, > + DRM_FORMAT_MOD_LINEAR, > + DRM_FORMAT_MOD_INVALID > +}; > + > static const uint64_t skl_format_modifiers[] = { Maybe calls this _ccs[] then? > + I915_FORMAT_MOD_Yf_TILED_CCS, > + I915_FORMAT_MOD_Y_TILED_CCS, > I915_FORMAT_MOD_Yf_TILED, > I915_FORMAT_MOD_Y_TILED, > I915_FORMAT_MOD_X_TILED, > @@ -13872,17 +13882,13 @@ static bool skl_mod_supported(uint32_t format, uint64_t modifier) > return false; > } > case DRM_FORMAT_RGB565: > - case DRM_FORMAT_XRGB8888: > - case DRM_FORMAT_XBGR8888: > - case DRM_FORMAT_ARGB8888: > - case DRM_FORMAT_ABGR8888: > case DRM_FORMAT_XRGB2101010: > case DRM_FORMAT_XBGR2101010: > case DRM_FORMAT_YUYV: > case DRM_FORMAT_YVYU: > case DRM_FORMAT_UYVY: > case DRM_FORMAT_VYUY: > - /* All i915 modifiers are fine */ > + /* All non-ccs i915 modifiers are fine */ > switch (modifier) { > case DRM_FORMAT_MOD_LINEAR: > case I915_FORMAT_MOD_X_TILED: > @@ -13892,6 +13898,12 @@ static bool skl_mod_supported(uint32_t format, uint64_t modifier) > default: > return false; > } > + case DRM_FORMAT_XRGB8888: > + case DRM_FORMAT_XBGR8888: > + case DRM_FORMAT_ARGB8888: > + case DRM_FORMAT_ABGR8888: > + /* All i915 modifiers are fine */ > + return true; > default: > return false; > } > @@ -14123,13 +14135,23 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) > primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); > primary->check_plane = intel_check_primary_plane; > > - if (INTEL_GEN(dev_priv) >= 9) { > + if (INTEL_GEN(dev_priv) >= 10) { > intel_primary_formats = skl_primary_formats; > num_formats = ARRAY_SIZE(skl_primary_formats); > intel_format_modifiers = skl_format_modifiers; > > primary->update_plane = skylake_update_primary_plane; > primary->disable_plane = skylake_disable_primary_plane; > + } else if (INTEL_GEN(dev_priv) >= 9) { > + intel_primary_formats = skl_primary_formats; > + num_formats = ARRAY_SIZE(skl_primary_formats); > + if (pipe >= PIPE_C) I think I'd keep the gen10 stuff in the same branch still. Also this misses GLK. So maybe something like this: if (GEN >= 10 || IS_GLK || pipe != PIPE_C) > + intel_format_modifiers = skl_format_modifiers; > + else > + intel_format_modifiers = skl_format_modifiers_noccs; > + > + primary->update_plane = skylake_update_primary_plane; > + primary->disable_plane = skylake_disable_primary_plane; > } else if (INTEL_GEN(dev_priv) >= 4) { > intel_primary_formats = i965_primary_formats; > num_formats = ARRAY_SIZE(i965_primary_formats); > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c > index e80834cb1f4c..de4454a8ef9e 100644 > --- a/drivers/gpu/drm/i915/intel_sprite.c > +++ b/drivers/gpu/drm/i915/intel_sprite.c > @@ -1085,7 +1085,17 @@ static uint32_t skl_plane_formats[] = { > DRM_FORMAT_VYUY, > }; > > +static const uint64_t skl_plane_format_modifiers_noccs[] = { > + I915_FORMAT_MOD_Yf_TILED, > + I915_FORMAT_MOD_Y_TILED, > + I915_FORMAT_MOD_X_TILED, > + DRM_FORMAT_MOD_LINEAR, > + DRM_FORMAT_MOD_INVALID > +}; > + > static const uint64_t skl_plane_format_modifiers[] = { Again _ccs[] maybe? > + I915_FORMAT_MOD_Yf_TILED_CCS, > + I915_FORMAT_MOD_Y_TILED_CCS, > I915_FORMAT_MOD_Yf_TILED, > I915_FORMAT_MOD_Y_TILED, > I915_FORMAT_MOD_X_TILED, > @@ -1108,6 +1118,20 @@ static bool intel_sprite_plane_format_mod_supported(struct drm_plane *plane, > modifier != DRM_FORMAT_MOD_LINEAR) > return false; > > + switch (modifier) { > + case I915_FORMAT_MOD_Yf_TILED_CCS: > + case I915_FORMAT_MOD_Y_TILED_CCS: > + switch (format) { > + case DRM_FORMAT_ABGR8888: > + case DRM_FORMAT_ARGB8888: > + case DRM_FORMAT_XBGR8888: > + case DRM_FORMAT_XRGB8888: > + return true; > + default: > + return false; > + } > + } > + > switch (format) { > case DRM_FORMAT_XBGR2101010: > case DRM_FORMAT_ABGR2101010: > @@ -1173,7 +1197,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, > } > intel_plane->base.state = &state->base; > > - if (INTEL_GEN(dev_priv) >= 9) { > + if (INTEL_GEN(dev_priv) >= 10) { > intel_plane->can_scale = true; > state->scaler_id = -1; > > @@ -1183,6 +1207,19 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, > plane_formats = skl_plane_formats; > num_plane_formats = ARRAY_SIZE(skl_plane_formats); > modifiers = skl_plane_format_modifiers; > + } else if (INTEL_GEN(dev_priv) >= 9) { > + intel_plane->can_scale = true; > + state->scaler_id = -1; > + > + intel_plane->update_plane = skl_update_plane; > + intel_plane->disable_plane = skl_disable_plane; > + > + plane_formats = skl_plane_formats; > + num_plane_formats = ARRAY_SIZE(skl_plane_formats); > + if (pipe >= PIPE_C) > + modifiers = skl_plane_format_modifiers_noccs; > + else > + modifiers = skl_plane_format_modifiers; > } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { > intel_plane->can_scale = false; > intel_plane->max_downscale = 1; > -- > 2.13.1 > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel
On 17-06-29 23:02:08, Ville Syrjälä wrote: >On Fri, Jun 23, 2017 at 09:45:44AM -0700, Ben Widawsky wrote: >> v2: >> Support sprite plane. >> Support pipe C/D limitation on GEN9. >> >> This requires rebase on the correct Ville patches >> >> Cc: Daniel Stone <daniels@collabora.com> >> Cc: Kristian Høgsberg <krh@bitplanet.net> >> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> >> --- >> drivers/gpu/drm/i915/intel_display.c | 34 +++++++++++++++++++++++++------ >> drivers/gpu/drm/i915/intel_sprite.c | 39 +++++++++++++++++++++++++++++++++++- >> 2 files changed, 66 insertions(+), 7 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c >> index 877a51514c61..2a0e5cd26059 100644 >> --- a/drivers/gpu/drm/i915/intel_display.c >> +++ b/drivers/gpu/drm/i915/intel_display.c >> @@ -93,7 +93,17 @@ static const uint32_t skl_primary_formats[] = { >> DRM_FORMAT_VYUY, >> }; >> >> +static const uint64_t skl_format_modifiers_noccs[] = { >> + I915_FORMAT_MOD_Yf_TILED, >> + I915_FORMAT_MOD_Y_TILED, >> + I915_FORMAT_MOD_X_TILED, >> + DRM_FORMAT_MOD_LINEAR, >> + DRM_FORMAT_MOD_INVALID >> +}; >> + >> static const uint64_t skl_format_modifiers[] = { > >Maybe calls this _ccs[] then? > >> + I915_FORMAT_MOD_Yf_TILED_CCS, >> + I915_FORMAT_MOD_Y_TILED_CCS, >> I915_FORMAT_MOD_Yf_TILED, >> I915_FORMAT_MOD_Y_TILED, >> I915_FORMAT_MOD_X_TILED, >> @@ -13872,17 +13882,13 @@ static bool skl_mod_supported(uint32_t format, uint64_t modifier) >> return false; >> } >> case DRM_FORMAT_RGB565: >> - case DRM_FORMAT_XRGB8888: >> - case DRM_FORMAT_XBGR8888: >> - case DRM_FORMAT_ARGB8888: >> - case DRM_FORMAT_ABGR8888: >> case DRM_FORMAT_XRGB2101010: >> case DRM_FORMAT_XBGR2101010: >> case DRM_FORMAT_YUYV: >> case DRM_FORMAT_YVYU: >> case DRM_FORMAT_UYVY: >> case DRM_FORMAT_VYUY: >> - /* All i915 modifiers are fine */ >> + /* All non-ccs i915 modifiers are fine */ >> switch (modifier) { >> case DRM_FORMAT_MOD_LINEAR: >> case I915_FORMAT_MOD_X_TILED: >> @@ -13892,6 +13898,12 @@ static bool skl_mod_supported(uint32_t format, uint64_t modifier) >> default: >> return false; >> } >> + case DRM_FORMAT_XRGB8888: >> + case DRM_FORMAT_XBGR8888: >> + case DRM_FORMAT_ARGB8888: >> + case DRM_FORMAT_ABGR8888: >> + /* All i915 modifiers are fine */ >> + return true; >> default: >> return false; >> } >> @@ -14123,13 +14135,23 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) >> primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); >> primary->check_plane = intel_check_primary_plane; >> >> - if (INTEL_GEN(dev_priv) >= 9) { >> + if (INTEL_GEN(dev_priv) >= 10) { >> intel_primary_formats = skl_primary_formats; >> num_formats = ARRAY_SIZE(skl_primary_formats); >> intel_format_modifiers = skl_format_modifiers; >> >> primary->update_plane = skylake_update_primary_plane; >> primary->disable_plane = skylake_disable_primary_plane; >> + } else if (INTEL_GEN(dev_priv) >= 9) { >> + intel_primary_formats = skl_primary_formats; >> + num_formats = ARRAY_SIZE(skl_primary_formats); >> + if (pipe >= PIPE_C) > >I think I'd keep the gen10 stuff in the same branch still. Also this >misses GLK. So maybe something like this: > >if (GEN >= 10 || IS_GLK || pipe != PIPE_C) > I'd really like to keep the pipe C limitation in the gen9 block, but yes, it was missing GLK. (Patches were originally written before GLK, I believe) Thanks for catching that. I really suspect we're going to need to split display version out of INTEL_GEN. Maybe you guys are already doing this. I'm fine with ccs rename, and you were right in the previous patch about how reorganizing made this diff nicer. >> + intel_format_modifiers = skl_format_modifiers; >> + else >> + intel_format_modifiers = skl_format_modifiers_noccs; >> + >> + primary->update_plane = skylake_update_primary_plane; >> + primary->disable_plane = skylake_disable_primary_plane; >> } else if (INTEL_GEN(dev_priv) >= 4) { >> intel_primary_formats = i965_primary_formats; >> num_formats = ARRAY_SIZE(i965_primary_formats); >> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c >> index e80834cb1f4c..de4454a8ef9e 100644 >> --- a/drivers/gpu/drm/i915/intel_sprite.c >> +++ b/drivers/gpu/drm/i915/intel_sprite.c >> @@ -1085,7 +1085,17 @@ static uint32_t skl_plane_formats[] = { >> DRM_FORMAT_VYUY, >> }; >> >> +static const uint64_t skl_plane_format_modifiers_noccs[] = { >> + I915_FORMAT_MOD_Yf_TILED, >> + I915_FORMAT_MOD_Y_TILED, >> + I915_FORMAT_MOD_X_TILED, >> + DRM_FORMAT_MOD_LINEAR, >> + DRM_FORMAT_MOD_INVALID >> +}; >> + >> static const uint64_t skl_plane_format_modifiers[] = { > >Again _ccs[] maybe? > >> + I915_FORMAT_MOD_Yf_TILED_CCS, >> + I915_FORMAT_MOD_Y_TILED_CCS, >> I915_FORMAT_MOD_Yf_TILED, >> I915_FORMAT_MOD_Y_TILED, >> I915_FORMAT_MOD_X_TILED, >> @@ -1108,6 +1118,20 @@ static bool intel_sprite_plane_format_mod_supported(struct drm_plane *plane, >> modifier != DRM_FORMAT_MOD_LINEAR) >> return false; >> >> + switch (modifier) { >> + case I915_FORMAT_MOD_Yf_TILED_CCS: >> + case I915_FORMAT_MOD_Y_TILED_CCS: >> + switch (format) { >> + case DRM_FORMAT_ABGR8888: >> + case DRM_FORMAT_ARGB8888: >> + case DRM_FORMAT_XBGR8888: >> + case DRM_FORMAT_XRGB8888: >> + return true; >> + default: >> + return false; >> + } >> + } >> + >> switch (format) { >> case DRM_FORMAT_XBGR2101010: >> case DRM_FORMAT_ABGR2101010: >> @@ -1173,7 +1197,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, >> } >> intel_plane->base.state = &state->base; >> >> - if (INTEL_GEN(dev_priv) >= 9) { >> + if (INTEL_GEN(dev_priv) >= 10) { >> intel_plane->can_scale = true; >> state->scaler_id = -1; >> >> @@ -1183,6 +1207,19 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, >> plane_formats = skl_plane_formats; >> num_plane_formats = ARRAY_SIZE(skl_plane_formats); >> modifiers = skl_plane_format_modifiers; >> + } else if (INTEL_GEN(dev_priv) >= 9) { >> + intel_plane->can_scale = true; >> + state->scaler_id = -1; >> + >> + intel_plane->update_plane = skl_update_plane; >> + intel_plane->disable_plane = skl_disable_plane; >> + >> + plane_formats = skl_plane_formats; >> + num_plane_formats = ARRAY_SIZE(skl_plane_formats); >> + if (pipe >= PIPE_C) >> + modifiers = skl_plane_format_modifiers_noccs; >> + else >> + modifiers = skl_plane_format_modifiers; >> } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { >> intel_plane->can_scale = false; >> intel_plane->max_downscale = 1; >> -- >> 2.13.1 >> >> _______________________________________________ >> dri-devel mailing list >> dri-devel@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/dri-devel > >-- >Ville Syrjälä >Intel OTC
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 877a51514c61..2a0e5cd26059 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -93,7 +93,17 @@ static const uint32_t skl_primary_formats[] = { DRM_FORMAT_VYUY, }; +static const uint64_t skl_format_modifiers_noccs[] = { + I915_FORMAT_MOD_Yf_TILED, + I915_FORMAT_MOD_Y_TILED, + I915_FORMAT_MOD_X_TILED, + DRM_FORMAT_MOD_LINEAR, + DRM_FORMAT_MOD_INVALID +}; + static const uint64_t skl_format_modifiers[] = { + I915_FORMAT_MOD_Yf_TILED_CCS, + I915_FORMAT_MOD_Y_TILED_CCS, I915_FORMAT_MOD_Yf_TILED, I915_FORMAT_MOD_Y_TILED, I915_FORMAT_MOD_X_TILED, @@ -13872,17 +13882,13 @@ static bool skl_mod_supported(uint32_t format, uint64_t modifier) return false; } case DRM_FORMAT_RGB565: - case DRM_FORMAT_XRGB8888: - case DRM_FORMAT_XBGR8888: - case DRM_FORMAT_ARGB8888: - case DRM_FORMAT_ABGR8888: case DRM_FORMAT_XRGB2101010: case DRM_FORMAT_XBGR2101010: case DRM_FORMAT_YUYV: case DRM_FORMAT_YVYU: case DRM_FORMAT_UYVY: case DRM_FORMAT_VYUY: - /* All i915 modifiers are fine */ + /* All non-ccs i915 modifiers are fine */ switch (modifier) { case DRM_FORMAT_MOD_LINEAR: case I915_FORMAT_MOD_X_TILED: @@ -13892,6 +13898,12 @@ static bool skl_mod_supported(uint32_t format, uint64_t modifier) default: return false; } + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_ARGB8888: + case DRM_FORMAT_ABGR8888: + /* All i915 modifiers are fine */ + return true; default: return false; } @@ -14123,13 +14135,23 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); primary->check_plane = intel_check_primary_plane; - if (INTEL_GEN(dev_priv) >= 9) { + if (INTEL_GEN(dev_priv) >= 10) { intel_primary_formats = skl_primary_formats; num_formats = ARRAY_SIZE(skl_primary_formats); intel_format_modifiers = skl_format_modifiers; primary->update_plane = skylake_update_primary_plane; primary->disable_plane = skylake_disable_primary_plane; + } else if (INTEL_GEN(dev_priv) >= 9) { + intel_primary_formats = skl_primary_formats; + num_formats = ARRAY_SIZE(skl_primary_formats); + if (pipe >= PIPE_C) + intel_format_modifiers = skl_format_modifiers; + else + intel_format_modifiers = skl_format_modifiers_noccs; + + primary->update_plane = skylake_update_primary_plane; + primary->disable_plane = skylake_disable_primary_plane; } else if (INTEL_GEN(dev_priv) >= 4) { intel_primary_formats = i965_primary_formats; num_formats = ARRAY_SIZE(i965_primary_formats); diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index e80834cb1f4c..de4454a8ef9e 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -1085,7 +1085,17 @@ static uint32_t skl_plane_formats[] = { DRM_FORMAT_VYUY, }; +static const uint64_t skl_plane_format_modifiers_noccs[] = { + I915_FORMAT_MOD_Yf_TILED, + I915_FORMAT_MOD_Y_TILED, + I915_FORMAT_MOD_X_TILED, + DRM_FORMAT_MOD_LINEAR, + DRM_FORMAT_MOD_INVALID +}; + static const uint64_t skl_plane_format_modifiers[] = { + I915_FORMAT_MOD_Yf_TILED_CCS, + I915_FORMAT_MOD_Y_TILED_CCS, I915_FORMAT_MOD_Yf_TILED, I915_FORMAT_MOD_Y_TILED, I915_FORMAT_MOD_X_TILED, @@ -1108,6 +1118,20 @@ static bool intel_sprite_plane_format_mod_supported(struct drm_plane *plane, modifier != DRM_FORMAT_MOD_LINEAR) return false; + switch (modifier) { + case I915_FORMAT_MOD_Yf_TILED_CCS: + case I915_FORMAT_MOD_Y_TILED_CCS: + switch (format) { + case DRM_FORMAT_ABGR8888: + case DRM_FORMAT_ARGB8888: + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_XRGB8888: + return true; + default: + return false; + } + } + switch (format) { case DRM_FORMAT_XBGR2101010: case DRM_FORMAT_ABGR2101010: @@ -1173,7 +1197,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, } intel_plane->base.state = &state->base; - if (INTEL_GEN(dev_priv) >= 9) { + if (INTEL_GEN(dev_priv) >= 10) { intel_plane->can_scale = true; state->scaler_id = -1; @@ -1183,6 +1207,19 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, plane_formats = skl_plane_formats; num_plane_formats = ARRAY_SIZE(skl_plane_formats); modifiers = skl_plane_format_modifiers; + } else if (INTEL_GEN(dev_priv) >= 9) { + intel_plane->can_scale = true; + state->scaler_id = -1; + + intel_plane->update_plane = skl_update_plane; + intel_plane->disable_plane = skl_disable_plane; + + plane_formats = skl_plane_formats; + num_plane_formats = ARRAY_SIZE(skl_plane_formats); + if (pipe >= PIPE_C) + modifiers = skl_plane_format_modifiers_noccs; + else + modifiers = skl_plane_format_modifiers; } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { intel_plane->can_scale = false; intel_plane->max_downscale = 1;
v2: Support sprite plane. Support pipe C/D limitation on GEN9. This requires rebase on the correct Ville patches Cc: Daniel Stone <daniels@collabora.com> Cc: Kristian Høgsberg <krh@bitplanet.net> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> --- drivers/gpu/drm/i915/intel_display.c | 34 +++++++++++++++++++++++++------ drivers/gpu/drm/i915/intel_sprite.c | 39 +++++++++++++++++++++++++++++++++++- 2 files changed, 66 insertions(+), 7 deletions(-)