| Message ID | 1501271035-8592-3-git-send-email-volodymyr_babchuk@epam.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi, On 07/28/2017 08:43 PM, Volodymyr Babchuk wrote: > On ARMv8, one of conditional exceptions (SMC that originates > from aarch32 state) have extra field in HCR.ISS encoding: > > CCKNOWNPASS, bit [19] > Indicates whether the instruction might have failed its condition > code check. > 0 - The instruction was unconditional, or was conditional and > passed its condition code check. > 1 - The instruction was conditional, and might have failed its > condition code check. Please mention the ARM ARM version and paragraph. > > Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> > --- > xen/include/asm-arm/processor.h | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h > index f640d54..0131e66 100644 > --- a/xen/include/asm-arm/processor.h > +++ b/xen/include/asm-arm/processor.h > @@ -434,7 +434,8 @@ union hsr { > > /* Common to all conditional exception classes (0x0N, except 0x00). */ When I read this comment, I understand that hsr_cond contains common bits for all condition exception. However, with your changes this is not true at all. > struct hsr_cond { > - unsigned long res0:20; /* Reserved */ > + unsigned long res0:19; /* Reserved */ > + unsigned long ccknownpass:1; /* Instruction passed conditional check */ > unsigned long cc:4; /* Condition Code */ > unsigned long ccvalid:1;/* CC Valid */ > unsigned long len:1; /* Instruction length */ > Cheers,
On 07/28/2017 09:31 PM, Julien Grall wrote: > Hi, > > On 07/28/2017 08:43 PM, Volodymyr Babchuk wrote: >> On ARMv8, one of conditional exceptions (SMC that originates >> from aarch32 state) have extra field in HCR.ISS encoding: >> >> CCKNOWNPASS, bit [19] >> Indicates whether the instruction might have failed its condition >> code check. >> 0 - The instruction was unconditional, or was conditional and >> passed its condition code check. >> 1 - The instruction was conditional, and might have failed its >> condition code check. > > Please mention the ARM ARM version and paragraph. > >> >> Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> >> --- >> xen/include/asm-arm/processor.h | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/xen/include/asm-arm/processor.h >> b/xen/include/asm-arm/processor.h >> index f640d54..0131e66 100644 >> --- a/xen/include/asm-arm/processor.h >> +++ b/xen/include/asm-arm/processor.h >> @@ -434,7 +434,8 @@ union hsr { >> /* Common to all conditional exception classes (0x0N, except >> 0x00). */ > > When I read this comment, I understand that hsr_cond contains common > bits for all condition exception. However, with your changes this is not > true at all. To complete here. I think you should directly use hsr.smc.ccknownpass rather than hsr.cond in patch #4 given that this field is SMC specific. > >> struct hsr_cond { >> - unsigned long res0:20; /* Reserved */ >> + unsigned long res0:19; /* Reserved */ >> + unsigned long ccknownpass:1; /* Instruction passed >> conditional check */ >> unsigned long cc:4; /* Condition Code */ >> unsigned long ccvalid:1;/* CC Valid */ >> unsigned long len:1; /* Instruction length */ >> > > Cheers, >
diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index f640d54..0131e66 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -434,7 +434,8 @@ union hsr { /* Common to all conditional exception classes (0x0N, except 0x00). */ struct hsr_cond { - unsigned long res0:20; /* Reserved */ + unsigned long res0:19; /* Reserved */ + unsigned long ccknownpass:1; /* Instruction passed conditional check */ unsigned long cc:4; /* Condition Code */ unsigned long ccvalid:1;/* CC Valid */ unsigned long len:1; /* Instruction length */
On ARMv8, one of conditional exceptions (SMC that originates from aarch32 state) have extra field in HCR.ISS encoding: CCKNOWNPASS, bit [19] Indicates whether the instruction might have failed its condition code check. 0 - The instruction was unconditional, or was conditional and passed its condition code check. 1 - The instruction was conditional, and might have failed its condition code check. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> --- xen/include/asm-arm/processor.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)