| Message ID | 1500624187-12165-1-git-send-email-zhangqing@rock-chips.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi Elaine, sorry this took a bit longer, but I didn't manage to find the time to respond properly until now. Am Freitag, 21. Juli 2017, 16:03:07 CEST schrieb Elaine Zhang: > Fractional dividers may have special requirements concerning numerator > and denominator selection that differ from just getting the best > approximation. > > For example on Rockchip socs the denominator must be at least 20 times > larger than the numerator to generate precise clock frequencies. > > Therefore add the ability to provide custom approximation functions, > approx = rockchip_fractional_special_approx; > but approx = NULL in the default case. > > RK document description: > 3.1.9 Fractional divider usage > To get specific frequency, clocks of I2S, SPDIF, UARTcan be generated by > fractional divider. Generally you must set that denominator is 20 times > larger than numerator to generate precise clock frequency. So the > fractional divider applies only to generate low frequency clock like > I2S, UART. > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> > --- > drivers/clk/clk-fractional-divider.c | 4 ++++ > drivers/clk/rockchip/clk.c | 20 ++++++++++++++++++++ > include/linux/clk-provider.h | 3 +++ > 3 files changed, 27 insertions(+) The code below does go into the right direction, but I'd really like to have the full approximation overrideable. The reason is that while on Rockchip SoCs it's enough to increase the parent rate, other socs might have completely different requirements when determining numerator and denominator. So I've taken the time and modified your patch into 2 that look like I would envision it - compile-tested only, so please test :-) But essentially it only moves some things around but should be functionally equivalent to your patch. I'll add the patches as replies to this mail. Two more things to keep in mind for the future below: > @@ -145,6 +148,7 @@ struct clk_hw *clk_hw_register_fractional_divider(struct device *dev, > fd->nmask = GENMASK(nwidth - 1, 0) << nshift; > fd->flags = clk_divider_flags; > fd->lock = lock; > + fd->approx = NULL; not needed, as fd is allocated via kzalloc, so this is already NULL. Also it is nicer to spell approximation full (which I've done in my rework) [...] > diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h > index a428aec36ace..807262375292 100644 > --- a/include/linux/clk-provider.h > +++ b/include/linux/clk-provider.h > @@ -564,6 +564,9 @@ struct clk_fractional_divider { > u8 nwidth; > u32 nmask; > u8 flags; > + void (*approx)(struct clk_hw *hw, Please keep the spacing in line with other elements. Somehow here spaces instead of a tab slipped in between void and (*appro... Heiko
diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c index aab904618eb6..ab2bc229ef2f 100644 --- a/drivers/clk/clk-fractional-divider.c +++ b/drivers/clk/clk-fractional-divider.c @@ -60,6 +60,9 @@ static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate, if (!rate || rate >= *parent_rate) return *parent_rate; + if (fd->approx) + fd->approx(hw, rate, parent_rate); + /* * Get rate closer to *parent_rate to guarantee there is no overflow * for m and n. In the result it will be the nearest rate left shifted @@ -145,6 +148,7 @@ struct clk_hw *clk_hw_register_fractional_divider(struct device *dev, fd->nmask = GENMASK(nwidth - 1, 0) << nshift; fd->flags = clk_divider_flags; fd->lock = lock; + fd->approx = NULL; fd->hw.init = &init; hw = &fd->hw; diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index fe1d393cf678..8b21c5b19107 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -164,6 +164,25 @@ static int rockchip_clk_frac_notifier_cb(struct notifier_block *nb, return notifier_from_errno(ret); } +/** + * fractional divider must set that denominator is 20 times larger than + * numerator to generate precise clock frequency. + */ +void rockchip_fractional_special_approx(struct clk_hw *hw, + unsigned long rate, + unsigned long *parent_rate) +{ + struct clk_hw *p_parent; + unsigned long p_rate, p_parent_rate; + + p_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); + if ((rate * 20 > p_rate) && (p_rate % rate != 0)) { + p_parent = clk_hw_get_parent(clk_hw_get_parent(hw)); + p_parent_rate = clk_hw_get_rate(p_parent); + *parent_rate = p_parent_rate; + } +} + static struct clk *rockchip_clk_register_frac_branch( struct rockchip_clk_provider *ctx, const char *name, const char *const *parent_names, u8 num_parents, @@ -210,6 +229,7 @@ static struct clk *rockchip_clk_register_frac_branch( div->nwidth = 16; div->nmask = GENMASK(div->nwidth - 1, 0) << div->nshift; div->lock = lock; + div->approx = rockchip_fractional_special_approx; div_ops = &clk_fractional_divider_ops; clk = clk_register_composite(NULL, name, parent_names, num_parents, diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index a428aec36ace..807262375292 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -564,6 +564,9 @@ struct clk_fractional_divider { u8 nwidth; u32 nmask; u8 flags; + void (*approx)(struct clk_hw *hw, + unsigned long rate, + unsigned long *parent_rate); spinlock_t *lock; };
Fractional dividers may have special requirements concerning numerator and denominator selection that differ from just getting the best approximation. For example on Rockchip socs the denominator must be at least 20 times larger than the numerator to generate precise clock frequencies. Therefore add the ability to provide custom approximation functions, approx = rockchip_fractional_special_approx; but approx = NULL in the default case. RK document description: 3.1.9 Fractional divider usage To get specific frequency, clocks of I2S, SPDIF, UARTcan be generated by fractional divider. Generally you must set that denominator is 20 times larger than numerator to generate precise clock frequency. So the fractional divider applies only to generate low frequency clock like I2S, UART. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- drivers/clk/clk-fractional-divider.c | 4 ++++ drivers/clk/rockchip/clk.c | 20 ++++++++++++++++++++ include/linux/clk-provider.h | 3 +++ 3 files changed, 27 insertions(+)