diff mbox

[3/8] drm/exynos: mixer: simplify {vp_video, mixer_graph}_buffer()

Message ID 20170809114857.4945-4-tjakobi@math.uni-bielefeld.de (mailing list archive)
State New, archived
Headers show

Commit Message

Tobias Jakobi Aug. 9, 2017, 11:48 a.m. UTC 
DRM core already checks the validity of the pixelformats, so we
can simplify the checks here. The same applies to the FB modifier,
which is now checked in common Exynos plane code.

Also rename the booleans to reflect what true/false actually
means.

Signed-off-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
---
 drivers/gpu/drm/exynos/exynos_mixer.c | 31 +++++++------------------------
 1 file changed, 7 insertions(+), 24 deletions(-)

Comments

Inki Dae Aug. 11, 2017, 8:04 a.m. UTC | #1 
2017년 08월 09일 20:48에 Tobias Jakobi 이(가) 쓴 글:
> DRM core already checks the validity of the pixelformats, so we
> can simplify the checks here. The same applies to the FB modifier,
> which is now checked in common Exynos plane code.
> 
> Also rename the booleans to reflect what true/false actually
> means.
> 
> Signed-off-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
> ---
>  drivers/gpu/drm/exynos/exynos_mixer.c | 31 +++++++------------------------
>  1 file changed, 7 insertions(+), 24 deletions(-)
> 
> diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
> index 4c894d97aba3..8d68de85bada 100644
> --- a/drivers/gpu/drm/exynos/exynos_mixer.c
> +++ b/drivers/gpu/drm/exynos/exynos_mixer.c
> @@ -484,32 +484,18 @@ static void vp_video_buffer(struct mixer_context *ctx,
>  	unsigned int priority = state->base.normalized_zpos + 1;
>  	unsigned long flags;
>  	dma_addr_t luma_addr[2], chroma_addr[2];
> -	bool tiled_mode = false;
> -	bool crcb_mode = false;
> +	bool is_tiled, is_nv21;
>  	u32 val;
>  
> -	switch (fb->format->format) {
> -	case DRM_FORMAT_NV12:
> -		crcb_mode = false;
> -		break;
> -	case DRM_FORMAT_NV21:
> -		crcb_mode = true;
> -		break;
> -	default:
> -		DRM_ERROR("pixel format for vp is wrong [%d].\n",
> -				fb->format->format);
> -		return;
> -	}
> -
> -	if (fb->modifier == DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
> -		tiled_mode = true;
> +	is_nv21 = (fb->format->format == DRM_FORMAT_NV21);
> +	is_tiled = (fb->modifier == DRM_FORMAT_MOD_SAMSUNG_64_32_TILE);
>  
>  	luma_addr[0] = exynos_drm_fb_dma_addr(fb, 0);
>  	chroma_addr[0] = exynos_drm_fb_dma_addr(fb, 1);
>  
>  	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
>  		__set_bit(MXR_BIT_INTERLACE, &ctx->flags);
> -		if (tiled_mode) {
> +		if (is_tiled) {
>  			luma_addr[1] = luma_addr[0] + 0x40;
>  			chroma_addr[1] = chroma_addr[0] + 0x40;
>  		} else {
> @@ -529,8 +515,8 @@ static void vp_video_buffer(struct mixer_context *ctx,
>  	vp_reg_writemask(res, VP_MODE, val, VP_MODE_LINE_SKIP);
>  
>  	/* setup format */
> -	val = (crcb_mode ? VP_MODE_NV21 : VP_MODE_NV12);
> -	val |= (tiled_mode ? VP_MODE_MEM_TILED : VP_MODE_MEM_LINEAR);
> +	val = (is_nv21 ? VP_MODE_NV21 : VP_MODE_NV12);
> +	val |= (is_tiled ? VP_MODE_MEM_TILED : VP_MODE_MEM_LINEAR);
>  	vp_reg_writemask(res, VP_MODE, val, VP_MODE_FMT_MASK);
>  
>  	/* setting size of input image */
> @@ -620,12 +606,9 @@ static void mixer_graph_buffer(struct mixer_context *ctx,
>  
>  	case DRM_FORMAT_XRGB8888:
>  	case DRM_FORMAT_ARGB8888:
> +	default:
>  		fmt = MXR_FORMAT_ARGB8888;
>  		break;
> -
> -	default:
> -		DRM_DEBUG_KMS("pixelformat unsupported by mixer\n");
> -		return;

This change should be made as another patch because this patch changes the behavior whether it allows wrong pixel format or not.

Thanks,
Inki Dae

>  	}
>  
>  	/* ratio is already checked by common plane code */
>
Tobias Jakobi Aug. 11, 2017, 11:43 a.m. UTC | #2 
Inki Dae wrote:
> 
> 
> 2017년 08월 09일 20:48에 Tobias Jakobi 이(가) 쓴 글:
>> DRM core already checks the validity of the pixelformats, so we
>> can simplify the checks here. The same applies to the FB modifier,
>> which is now checked in common Exynos plane code.
>>
>> Also rename the booleans to reflect what true/false actually
>> means.
>>
>> Signed-off-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
>> ---
>>  drivers/gpu/drm/exynos/exynos_mixer.c | 31 +++++++------------------------
>>  1 file changed, 7 insertions(+), 24 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
>> index 4c894d97aba3..8d68de85bada 100644
>> --- a/drivers/gpu/drm/exynos/exynos_mixer.c
>> +++ b/drivers/gpu/drm/exynos/exynos_mixer.c
>> @@ -484,32 +484,18 @@ static void vp_video_buffer(struct mixer_context *ctx,
>>  	unsigned int priority =tate->base.normalized_zpos + 1;
>>  	unsigned long flags;
>>  	dma_addr_t luma_addr[2], chroma_addr[2];
>> -	bool tiled_mode =alse;
>> -	bool crcb_mode =alse;
>> +	bool is_tiled, is_nv21;
>>  	u32 val;
>>  
>> -	switch (fb->format->format) {
>> -	case DRM_FORMAT_NV12:
>> -		crcb_mode =alse;
>> -		break;
>> -	case DRM_FORMAT_NV21:
>> -		crcb_mode =rue;
>> -		break;
>> -	default:
>> -		DRM_ERROR("pixel format for vp is wrong [%d].\n",
>> -				fb->format->format);
>> -		return;
>> -	}
>> -
>> -	if (fb->modifier =DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
>> -		tiled_mode =rue;
>> +	is_nv21 =fb->format->format == DRM_FORMAT_NV21);
>> +	is_tiled =fb->modifier == DRM_FORMAT_MOD_SAMSUNG_64_32_TILE);
>>  
>>  	luma_addr[0] =xynos_drm_fb_dma_addr(fb, 0);
>>  	chroma_addr[0] =xynos_drm_fb_dma_addr(fb, 1);
>>  
>>  	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
>>  		__set_bit(MXR_BIT_INTERLACE, &ctx->flags);
>> -		if (tiled_mode) {
>> +		if (is_tiled) {
>>  			luma_addr[1] =uma_addr[0] + 0x40;
>>  			chroma_addr[1] =hroma_addr[0] + 0x40;
>>  		} else {
>> @@ -529,8 +515,8 @@ static void vp_video_buffer(struct mixer_context *ctx,
>>  	vp_reg_writemask(res, VP_MODE, val, VP_MODE_LINE_SKIP);
>>  
>>  	/* setup format */
>> -	val =crcb_mode ? VP_MODE_NV21 : VP_MODE_NV12);
>> -	val |=tiled_mode ? VP_MODE_MEM_TILED : VP_MODE_MEM_LINEAR);
>> +	val =is_nv21 ? VP_MODE_NV21 : VP_MODE_NV12);
>> +	val |=is_tiled ? VP_MODE_MEM_TILED : VP_MODE_MEM_LINEAR);
>>  	vp_reg_writemask(res, VP_MODE, val, VP_MODE_FMT_MASK);
>>  
>>  	/* setting size of input image */
>> @@ -620,12 +606,9 @@ static void mixer_graph_buffer(struct mixer_context *ctx,
>>  
>>  	case DRM_FORMAT_XRGB8888:
>>  	case DRM_FORMAT_ARGB8888:
>> +	default:
>>  		fmt =XR_FORMAT_ARGB8888;
>>  		break;
>> -
>> -	default:
>> -		DRM_DEBUG_KMS("pixelformat unsupported by mixer\n");
>> -		return;
> 
> This change should be made as another patch because this patch changes the behavior whether it allows wrong pixel format or not.
> 
OK, I will split the change to mixer_graph_buffer() into another patch here.

- Tobias


> Thanks,
> Inki Dae
> 
>>  	}
>>  
>>  	/* ratio is already checked by common plane code */
>>
> --
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>
diff mbox

Patch

diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
index 4c894d97aba3..8d68de85bada 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -484,32 +484,18 @@  static void vp_video_buffer(struct mixer_context *ctx,
 	unsigned int priority = state->base.normalized_zpos + 1;
 	unsigned long flags;
 	dma_addr_t luma_addr[2], chroma_addr[2];
-	bool tiled_mode = false;
-	bool crcb_mode = false;
+	bool is_tiled, is_nv21;
 	u32 val;
 
-	switch (fb->format->format) {
-	case DRM_FORMAT_NV12:
-		crcb_mode = false;
-		break;
-	case DRM_FORMAT_NV21:
-		crcb_mode = true;
-		break;
-	default:
-		DRM_ERROR("pixel format for vp is wrong [%d].\n",
-				fb->format->format);
-		return;
-	}
-
-	if (fb->modifier == DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
-		tiled_mode = true;
+	is_nv21 = (fb->format->format == DRM_FORMAT_NV21);
+	is_tiled = (fb->modifier == DRM_FORMAT_MOD_SAMSUNG_64_32_TILE);
 
 	luma_addr[0] = exynos_drm_fb_dma_addr(fb, 0);
 	chroma_addr[0] = exynos_drm_fb_dma_addr(fb, 1);
 
 	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 		__set_bit(MXR_BIT_INTERLACE, &ctx->flags);
-		if (tiled_mode) {
+		if (is_tiled) {
 			luma_addr[1] = luma_addr[0] + 0x40;
 			chroma_addr[1] = chroma_addr[0] + 0x40;
 		} else {
@@ -529,8 +515,8 @@  static void vp_video_buffer(struct mixer_context *ctx,
 	vp_reg_writemask(res, VP_MODE, val, VP_MODE_LINE_SKIP);
 
 	/* setup format */
-	val = (crcb_mode ? VP_MODE_NV21 : VP_MODE_NV12);
-	val |= (tiled_mode ? VP_MODE_MEM_TILED : VP_MODE_MEM_LINEAR);
+	val = (is_nv21 ? VP_MODE_NV21 : VP_MODE_NV12);
+	val |= (is_tiled ? VP_MODE_MEM_TILED : VP_MODE_MEM_LINEAR);
 	vp_reg_writemask(res, VP_MODE, val, VP_MODE_FMT_MASK);
 
 	/* setting size of input image */
@@ -620,12 +606,9 @@  static void mixer_graph_buffer(struct mixer_context *ctx,
 
 	case DRM_FORMAT_XRGB8888:
 	case DRM_FORMAT_ARGB8888:
+	default:
 		fmt = MXR_FORMAT_ARGB8888;
 		break;
-
-	default:
-		DRM_DEBUG_KMS("pixelformat unsupported by mixer\n");
-		return;
 	}
 
 	/* ratio is already checked by common plane code */