diff mbox

[v4,04/11] arm: processor.h: add definition for immediate value mask

Message ID 1503347275-13039-5-git-send-email-volodymyr_babchuk@epam.com (mailing list archive)
State New, archived
Headers show

Commit Message

Volodymyr Babchuk Aug. 21, 2017, 8:27 p.m. UTC 
This patch adds definition HSR_XXC_IMM_MASK. It can be used to extract
immediate value for trapped HVC32, HVC64, SMC64, SVC32, SVC64 instructions,
as described at ARM ARM (ARM DDI 0487B.a pages D7-2270, D7-2272).

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
---
 xen/include/asm-arm/processor.h | 3 +++
 1 file changed, 3 insertions(+)

Comments

Julien Grall Aug. 24, 2017, 2:45 p.m. UTC | #1 
Hi Volodymyr,

Title: It is a too generic, you may want to rename to: "Define HVC/SMC 
immediate mask"

On 21/08/17 21:27, Volodymyr Babchuk wrote:
> This patch adds definition HSR_XXC_IMM_MASK. It can be used to extract

s/adds definition/define/

> immediate value for trapped HVC32, HVC64, SMC64, SVC32, SVC64 instructions,
> as described at ARM ARM (ARM DDI 0487B.a pages D7-2270, D7-2272).

s/at/in the/

>
> Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
> ---
>  xen/include/asm-arm/processor.h | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
> index 51ce802..89752a7 100644
> --- a/xen/include/asm-arm/processor.h
> +++ b/xen/include/asm-arm/processor.h
> @@ -580,6 +580,9 @@ union hsr {
>                                HSR_SYSREG_CRN_MASK|HSR_SYSREG_CRM_MASK|\
>                                HSR_SYSREG_OP2_MASK)
>
> +/* HSR.EC == HSR_{HVC32, HVC64, SMC64, SVC32, SVC64} */
> +#define HSR_XXC_IMM_MASK     (0xffff)
> +
>  /* Physical Address Register */
>  #define PAR_F           (_AC(1,U)<<0)
>
>

Cheers,
diff mbox

Patch

diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index 51ce802..89752a7 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -580,6 +580,9 @@  union hsr {
                               HSR_SYSREG_CRN_MASK|HSR_SYSREG_CRM_MASK|\
                               HSR_SYSREG_OP2_MASK)
 
+/* HSR.EC == HSR_{HVC32, HVC64, SMC64, SVC32, SVC64} */
+#define HSR_XXC_IMM_MASK     (0xffff)
+
 /* Physical Address Register */
 #define PAR_F           (_AC(1,U)<<0)