| Message ID | 20170822031934.8675-4-jeffy.chen@rock-chips.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Aug 22, 2017 at 11:19:33AM +0800, Jeffy Chen wrote: > Add an optional interrupt for PCIE_WAKE pin. Rob? > Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> > --- > > Changes in v4: None > Changes in v3: None > Changes in v2: None > > .../devicetree/bindings/pci/rockchip-pcie.txt | 20 ++++++++++++-------- > 1 file changed, 12 insertions(+), 8 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt > index 5678be82530d..9f6504129e80 100644 > --- a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt > +++ b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt > @@ -20,10 +20,13 @@ Required properties: > - msi-map: Maps a Requester ID to an MSI controller and associated > msi-specifier data. See ./pci-msi.txt > - interrupts: Three interrupt entries must be specified. > -- interrupt-names: Must include the following names > - - "sys" > - - "legacy" > - - "client" > +- interrupt-names: Include the following names > + Required: > + - "sys" > + - "legacy" > + - "client" > + Optional: > + - "wake" Why is there no other PCI binding that includes "wake" as an interrupt-name? This feels like something that should be fairly common across host controllers. I don't want a Rockport-specific DT description if it could be made more general. > - resets: Must contain seven entries for each entry in reset-names. > See ../reset/reset.txt for details. > - reset-names: Must include the following names > @@ -87,10 +90,11 @@ pcie0: pcie@f8000000 { > clock-names = "aclk", "aclk-perf", > "hclk", "pm"; > bus-range = <0x0 0x1>; > - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, > - <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, > - <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; > - interrupt-names = "sys", "legacy", "client"; > + interrupts-extended = <&gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, > + <&gic GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, > + <&gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>, > + <&gpio0 8 IRQ_TYPE_LEVEL_LOW>; > + interrupt-names = "sys", "legacy", "client", "wake"; > assigned-clocks = <&cru SCLK_PCIEPHY_REF>; > assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; > assigned-clock-rates = <100000000>; > -- > 2.11.0 > >
On Thu, Aug 24, 2017 at 11:53:54AM -0500, Bjorn Helgaas wrote: > On Tue, Aug 22, 2017 at 11:19:33AM +0800, Jeffy Chen wrote: > > Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> > > diff --git a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt > > index 5678be82530d..9f6504129e80 100644 > > --- a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt > > +++ b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt > > @@ -20,10 +20,13 @@ Required properties: > > - msi-map: Maps a Requester ID to an MSI controller and associated > > msi-specifier data. See ./pci-msi.txt > > - interrupts: Three interrupt entries must be specified. > > -- interrupt-names: Must include the following names > > - - "sys" > > - - "legacy" > > - - "client" > > +- interrupt-names: Include the following names > > + Required: > > + - "sys" > > + - "legacy" > > + - "client" > > + Optional: > > + - "wake" > > Why is there no other PCI binding that includes "wake" as an > interrupt-name? This feels like something that should be fairly > common across host controllers. I don't want a Rockport-specific s/port/chip/ :) > DT description if it could be made more general. I'm not sure we can really answer that question ("why do no other PCI bindings have this?"). But one guess would be that every other controller uses only beacon wake. It would be OK with me if we made a blanket statement that a controller with a "wake" interrupt means PCI WAKE# (per the specification). It's possible this could even be stuck into some generic PCI/DT code eventually. (I don't think we have a really good place for this today.) Brian > > - resets: Must contain seven entries for each entry in reset-names. > > See ../reset/reset.txt for details. > > - reset-names: Must include the following names > > @@ -87,10 +90,11 @@ pcie0: pcie@f8000000 { > > clock-names = "aclk", "aclk-perf", > > "hclk", "pm"; > > bus-range = <0x0 0x1>; > > - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, > > - <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, > > - <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; > > - interrupt-names = "sys", "legacy", "client"; > > + interrupts-extended = <&gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, > > + <&gic GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, > > + <&gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>, > > + <&gpio0 8 IRQ_TYPE_LEVEL_LOW>; > > + interrupt-names = "sys", "legacy", "client", "wake"; > > assigned-clocks = <&cru SCLK_PCIEPHY_REF>; > > assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; > > assigned-clock-rates = <100000000>; > > -- > > 2.11.0 > > > >
On 2017/8/25 10:11, Brian Norris wrote: > On Thu, Aug 24, 2017 at 11:53:54AM -0500, Bjorn Helgaas wrote: >> On Tue, Aug 22, 2017 at 11:19:33AM +0800, Jeffy Chen wrote: >>> Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> > >>> diff --git a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt >>> index 5678be82530d..9f6504129e80 100644 >>> --- a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt >>> +++ b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt >>> @@ -20,10 +20,13 @@ Required properties: >>> - msi-map: Maps a Requester ID to an MSI controller and associated >>> msi-specifier data. See ./pci-msi.txt >>> - interrupts: Three interrupt entries must be specified. >>> -- interrupt-names: Must include the following names >>> - - "sys" >>> - - "legacy" >>> - - "client" >>> +- interrupt-names: Include the following names >>> + Required: >>> + - "sys" >>> + - "legacy" >>> + - "client" >>> + Optional: >>> + - "wake" >> >> Why is there no other PCI binding that includes "wake" as an >> interrupt-name? This feels like something that should be fairly >> common across host controllers. I don't want a Rockport-specific > > s/port/chip/ :) > >> DT description if it could be made more general. > > I'm not sure we can really answer that question ("why do no other PCI > bindings have this?"). But one guess would be that every other > controller uses only beacon wake. > > It would be OK with me if we made a blanket statement that a controller > with a "wake" interrupt means PCI WAKE# (per the specification). It's > possible this could even be stuck into some generic PCI/DT code > eventually. (I don't think we have a really good place for this today.) I guess we could register a pcie port service for dedicated WAKE# as it seems fairly parallel to pme code there, if we need a common place for that? > > Brian > >>> - resets: Must contain seven entries for each entry in reset-names. >>> See ../reset/reset.txt for details. >>> - reset-names: Must include the following names >>> @@ -87,10 +90,11 @@ pcie0: pcie@f8000000 { >>> clock-names = "aclk", "aclk-perf", >>> "hclk", "pm"; >>> bus-range = <0x0 0x1>; >>> - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, >>> - <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, >>> - <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; >>> - interrupt-names = "sys", "legacy", "client"; >>> + interrupts-extended = <&gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, >>> + <&gic GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, >>> + <&gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>, >>> + <&gpio0 8 IRQ_TYPE_LEVEL_LOW>; >>> + interrupt-names = "sys", "legacy", "client", "wake"; >>> assigned-clocks = <&cru SCLK_PCIEPHY_REF>; >>> assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; >>> assigned-clock-rates = <100000000>; >>> -- >>> 2.11.0 >>> >>> > > >
On Thu, Aug 24, 2017 at 07:11:32PM -0700, Brian Norris wrote: > On Thu, Aug 24, 2017 at 11:53:54AM -0500, Bjorn Helgaas wrote: > > On Tue, Aug 22, 2017 at 11:19:33AM +0800, Jeffy Chen wrote: > > > Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> > > > > diff --git a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt > > > index 5678be82530d..9f6504129e80 100644 > > > --- a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt > > > +++ b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt > > > @@ -20,10 +20,13 @@ Required properties: > > > - msi-map: Maps a Requester ID to an MSI controller and associated > > > msi-specifier data. See ./pci-msi.txt > > > - interrupts: Three interrupt entries must be specified. > > > -- interrupt-names: Must include the following names > > > - - "sys" > > > - - "legacy" > > > - - "client" > > > +- interrupt-names: Include the following names > > > + Required: > > > + - "sys" > > > + - "legacy" > > > + - "client" > > > + Optional: > > > + - "wake" > > > > Why is there no other PCI binding that includes "wake" as an > > interrupt-name? This feels like something that should be fairly > > common across host controllers. I don't want a Rockport-specific > > s/port/chip/ :) I visited Rockport this summer, guess I had it on the brain :) > > DT description if it could be made more general. > > I'm not sure we can really answer that question ("why do no other PCI > bindings have this?"). But one guess would be that every other > controller uses only beacon wake. > > It would be OK with me if we made a blanket statement that a controller > with a "wake" interrupt means PCI WAKE# (per the specification). It's > possible this could even be stuck into some generic PCI/DT code > eventually. (I don't think we have a really good place for this today.) I'd just like every controller that uses WAKE# to use the same name in DT. Maybe all that means for now is mentioning it in Documentation/devicetree/bindings/pci/pci.txt instead of (or in addition to) Documentation/devicetree/bindings/pci/rockchip-pcie.txt
On Tue, Aug 22, 2017 at 11:19:33AM +0800, Jeffy Chen wrote: > Add an optional interrupt for PCIE_WAKE pin. > > Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> > --- > > Changes in v4: None > Changes in v3: None > Changes in v2: None > > .../devicetree/bindings/pci/rockchip-pcie.txt | 20 ++++++++++++-------- > 1 file changed, 12 insertions(+), 8 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt > index 5678be82530d..9f6504129e80 100644 > --- a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt > +++ b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt > @@ -20,10 +20,13 @@ Required properties: > - msi-map: Maps a Requester ID to an MSI controller and associated > msi-specifier data. See ./pci-msi.txt > - interrupts: Three interrupt entries must be specified. > -- interrupt-names: Must include the following names > - - "sys" > - - "legacy" > - - "client" > +- interrupt-names: Include the following names > + Required: > + - "sys" > + - "legacy" > + - "client" > + Optional: > + - "wake" Use the wakeup source binding: Documentation/devicetree/bindings/power/wakeup-source.txt Rob
On Fri, Aug 25, 2017 at 01:14:39PM -0500, Rob Herring wrote: > On Tue, Aug 22, 2017 at 11:19:33AM +0800, Jeffy Chen wrote: > > Add an optional interrupt for PCIE_WAKE pin. > > > > Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> > > --- > > > > Changes in v4: None > > Changes in v3: None > > Changes in v2: None > > > > .../devicetree/bindings/pci/rockchip-pcie.txt | 20 ++++++++++++-------- > > 1 file changed, 12 insertions(+), 8 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt > > index 5678be82530d..9f6504129e80 100644 > > --- a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt > > +++ b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt > > @@ -20,10 +20,13 @@ Required properties: > > - msi-map: Maps a Requester ID to an MSI controller and associated > > msi-specifier data. See ./pci-msi.txt > > - interrupts: Three interrupt entries must be specified. > > -- interrupt-names: Must include the following names > > - - "sys" > > - - "legacy" > > - - "client" > > +- interrupt-names: Include the following names > > + Required: > > + - "sys" > > + - "legacy" > > + - "client" > > + Optional: > > + - "wake" > > Use the wakeup source binding: > Documentation/devicetree/bindings/power/wakeup-source.txt And I suppose this means we'd fall under this paragraph? "However if the devices have dedicated interrupt as the wakeup source then they need to specify/identify the same using device specific interrupt name. In such cases only that interrupt can be used as wakeup interrupt." We don't expect *any* interrupt to qualify as PCI WAKE#; so we should still also document the interrupt name ("wake"?) in Documentation/devicetree/bindings/pci/pci.txt as Bjorn suggested, in addition to using the 'wakeup-source' property documented there. Brian
On Fri, Aug 25, 2017 at 1:20 PM, Brian Norris <briannorris@chromium.org> wrote: > On Fri, Aug 25, 2017 at 01:14:39PM -0500, Rob Herring wrote: >> On Tue, Aug 22, 2017 at 11:19:33AM +0800, Jeffy Chen wrote: >> > Add an optional interrupt for PCIE_WAKE pin. >> > >> > Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> >> > --- >> > >> > Changes in v4: None >> > Changes in v3: None >> > Changes in v2: None >> > >> > .../devicetree/bindings/pci/rockchip-pcie.txt | 20 ++++++++++++-------- >> > 1 file changed, 12 insertions(+), 8 deletions(-) >> > >> > diff --git a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt >> > index 5678be82530d..9f6504129e80 100644 >> > --- a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt >> > +++ b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt >> > @@ -20,10 +20,13 @@ Required properties: >> > - msi-map: Maps a Requester ID to an MSI controller and associated >> > msi-specifier data. See ./pci-msi.txt >> > - interrupts: Three interrupt entries must be specified. >> > -- interrupt-names: Must include the following names >> > - - "sys" >> > - - "legacy" >> > - - "client" >> > +- interrupt-names: Include the following names >> > + Required: >> > + - "sys" >> > + - "legacy" >> > + - "client" >> > + Optional: >> > + - "wake" >> >> Use the wakeup source binding: >> Documentation/devicetree/bindings/power/wakeup-source.txt > > And I suppose this means we'd fall under this paragraph? > > "However if the devices have dedicated interrupt as the wakeup source > then they need to specify/identify the same using device specific > interrupt name. In such cases only that interrupt can be used as wakeup > interrupt." > > We don't expect *any* interrupt to qualify as PCI WAKE#; so we should > still also document the interrupt name ("wake"?) in > Documentation/devicetree/bindings/pci/pci.txt as Bjorn suggested, in > addition to using the 'wakeup-source' property documented there. I believe the defined interrupt name is "wakeup" as example 1 shows. Rob
On Mon, Aug 28, 2017 at 04:32:55PM -0500, Rob Herring wrote: > On Fri, Aug 25, 2017 at 1:20 PM, Brian Norris <briannorris@chromium.org> wrote: > > On Fri, Aug 25, 2017 at 01:14:39PM -0500, Rob Herring wrote: > >> Use the wakeup source binding: > >> Documentation/devicetree/bindings/power/wakeup-source.txt > > > > And I suppose this means we'd fall under this paragraph? > > > > "However if the devices have dedicated interrupt as the wakeup source > > then they need to specify/identify the same using device specific > > interrupt name. In such cases only that interrupt can be used as wakeup > > interrupt." > > > > We don't expect *any* interrupt to qualify as PCI WAKE#; so we should > > still also document the interrupt name ("wake"?) in > > Documentation/devicetree/bindings/pci/pci.txt as Bjorn suggested, in > > addition to using the 'wakeup-source' property documented there. > > I believe the defined interrupt name is "wakeup" as example 1 shows. That's an example, not a definition. And the definition I quoted literally says "device specific interrupt name". The PCIe specification calls it "WAKE#" all over the place, so I figured that's a good name to use. "wakeup" is also fine I suppose, as long as we document that it must be PCIe WAKE# signal, as per the PCIe specfication. Brian
diff --git a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt index 5678be82530d..9f6504129e80 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt +++ b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt @@ -20,10 +20,13 @@ Required properties: - msi-map: Maps a Requester ID to an MSI controller and associated msi-specifier data. See ./pci-msi.txt - interrupts: Three interrupt entries must be specified. -- interrupt-names: Must include the following names - - "sys" - - "legacy" - - "client" +- interrupt-names: Include the following names + Required: + - "sys" + - "legacy" + - "client" + Optional: + - "wake" - resets: Must contain seven entries for each entry in reset-names. See ../reset/reset.txt for details. - reset-names: Must include the following names @@ -87,10 +90,11 @@ pcie0: pcie@f8000000 { clock-names = "aclk", "aclk-perf", "hclk", "pm"; bus-range = <0x0 0x1>; - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; - interrupt-names = "sys", "legacy", "client"; + interrupts-extended = <&gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, + <&gic GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, + <&gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>, + <&gpio0 8 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "sys", "legacy", "client", "wake"; assigned-clocks = <&cru SCLK_PCIEPHY_REF>; assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; assigned-clock-rates = <100000000>;
Add an optional interrupt for PCIE_WAKE pin. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> --- Changes in v4: None Changes in v3: None Changes in v2: None .../devicetree/bindings/pci/rockchip-pcie.txt | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-)