diff mbox

[v5,04/10] arm: processor.h: add definition for immediate value mask

Message ID 1504210172-27234-5-git-send-email-volodymyr_babchuk@epam.com (mailing list archive)
State New, archived
Headers show

Commit Message

Volodymyr Babchuk Aug. 31, 2017, 8:09 p.m. UTC 
This patch define HSR_XXC_IMM_MASK. It can be used to extract
immediate value for trapped HVC32, HVC64, SMC64, SVC32, SVC64
instructions, as described in the ARM ARM
(ARM DDI 0487B.a pages D7-2270, D7-2272).

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
---

 * spelling fixes

---
 xen/include/asm-arm/processor.h | 3 +++
 1 file changed, 3 insertions(+)

Comments

Julien Grall Sept. 13, 2017, 10:02 a.m. UTC | #1 
Hi Volodymyr,

On 08/31/2017 09:09 PM, Volodymyr Babchuk wrote:
> This patch define HSR_XXC_IMM_MASK. It can be used to extract

NIT: s/define/defines/

> immediate value for trapped HVC32, HVC64, SMC64, SVC32, SVC64
> instructions, as described in the ARM ARM
> (ARM DDI 0487B.a pages D7-2270, D7-2272).
> 
> Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>

Acked-by: Julien Grall <julien.grall@arm.com>

Cheers,

> ---
> 
>   * spelling fixes
> 
> ---
>   xen/include/asm-arm/processor.h | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
> index 51ce802..89752a7 100644
> --- a/xen/include/asm-arm/processor.h
> +++ b/xen/include/asm-arm/processor.h
> @@ -580,6 +580,9 @@ union hsr {
>                                 HSR_SYSREG_CRN_MASK|HSR_SYSREG_CRM_MASK|\
>                                 HSR_SYSREG_OP2_MASK)
>   
> +/* HSR.EC == HSR_{HVC32, HVC64, SMC64, SVC32, SVC64} */
> +#define HSR_XXC_IMM_MASK     (0xffff)
> +
>   /* Physical Address Register */
>   #define PAR_F           (_AC(1,U)<<0)
>   
>
diff mbox

Patch

diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index 51ce802..89752a7 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -580,6 +580,9 @@  union hsr {
                               HSR_SYSREG_CRN_MASK|HSR_SYSREG_CRM_MASK|\
                               HSR_SYSREG_OP2_MASK)
 
+/* HSR.EC == HSR_{HVC32, HVC64, SMC64, SVC32, SVC64} */
+#define HSR_XXC_IMM_MASK     (0xffff)
+
 /* Physical Address Register */
 #define PAR_F           (_AC(1,U)<<0)