| Message ID | 20170912100330.2168-6-julien.grall@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, 12 Sep 2017, Julien Grall wrote: > Signed-off-by: Julien Grall <julien.grall@arm.com> > Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Stefano Stabellini <sstabellini@kernel.org> > --- > > Note that the missing FnV bits present ARMv8 will be added in a > follow-up patch. > > Changes in v2: > - Add Andre's reviewed-by > --- > xen/include/asm-arm/processor.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h > index 9f7a42f86b..bea4a56190 100644 > --- a/xen/include/asm-arm/processor.h > +++ b/xen/include/asm-arm/processor.h > @@ -583,9 +583,9 @@ union hsr { > > struct hsr_iabt { > unsigned long ifsc:6; /* Instruction fault status code */ > - unsigned long res0:1; > + unsigned long res0:1; /* RES0 */ > unsigned long s1ptw:1; /* Stage 2 fault during stage 1 translation */ > - unsigned long res1:1; > + unsigned long res1:1; /* RES0 */ > unsigned long eat:1; /* External abort type */ > unsigned long res2:15; > unsigned long len:1; /* Instruction length */
On Tue, 12 Sep 2017, Julien Grall wrote: > Aliasing FAR_EL2 to HIFAR makes the code confusing because on ARMv8 > FAR_EL2[31:0] is architecturally mapped to HDFAR and FAR_EL2[63:32] to > HIFAR. See D7.2.30 in ARM DDI 0487B.a. Open-code the alias instead. > > Signed-off-by: Julien Grall <julien.grall@arm.com> > Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Stefano Stabellini <sstabellini@kernel.org> > --- > Changes in v2: > - Fix register name in the commit message > - Add Andre's reviewed-by > --- > xen/arch/arm/traps.c | 8 +++++++- > xen/include/asm-arm/cpregs.h | 1 - > 2 files changed, 7 insertions(+), 2 deletions(-) > > diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c > index 7f6ec15b5e..967bfea4ed 100644 > --- a/xen/arch/arm/traps.c > +++ b/xen/arch/arm/traps.c > @@ -2579,11 +2579,17 @@ static void do_trap_instr_abort_guest(struct cpu_user_regs *regs, > const union hsr hsr) > { > int rc; > - register_t gva = READ_SYSREG(FAR_EL2); > + register_t gva; > uint8_t fsc = hsr.iabt.ifsc & ~FSC_LL_MASK; > paddr_t gpa; > mfn_t mfn; > > +#ifdef CONFIG_ARM_32 > + gva = READ_CP32(HIFAR); > +#else > + gva = READ_SYSREG64(FAR_EL2); > +#endif > + > /* > * If this bit has been set, it means that this instruction abort is caused > * by a guest external abort. We can handle this instruction abort as guest > diff --git a/xen/include/asm-arm/cpregs.h b/xen/include/asm-arm/cpregs.h > index af45ec7a65..1889d7cbfb 100644 > --- a/xen/include/asm-arm/cpregs.h > +++ b/xen/include/asm-arm/cpregs.h > @@ -307,7 +307,6 @@ > #define ESR_EL1 DFSR > #define ESR_EL2 HSR > #define FAR_EL1 HIFAR > -#define FAR_EL2 HIFAR > #define HCR_EL2 HCR > #define HPFAR_EL2 HPFAR > #define HSTR_EL2 HSTR > -- > 2.11.0 >
diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index 9f7a42f86b..bea4a56190 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -583,9 +583,9 @@ union hsr { struct hsr_iabt { unsigned long ifsc:6; /* Instruction fault status code */ - unsigned long res0:1; + unsigned long res0:1; /* RES0 */ unsigned long s1ptw:1; /* Stage 2 fault during stage 1 translation */ - unsigned long res1:1; + unsigned long res1:1; /* RES0 */ unsigned long eat:1; /* External abort type */ unsigned long res2:15; unsigned long len:1; /* Instruction length */