| Message ID | 1506095916-20250-1-git-send-email-vathsala.nagaraju@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Sep 22, 2017 at 03:58:36PM +0000, vathsala nagaraju wrote: > Set frames before SU entry value for max resync frame count of > dpcd register 2009, bit field 0:3. > > v2 : > - add macro EDP_PSR2_FRAME_BEFORE_SU (Rodrigo) > - remove EDP_FRAMES_BEFORE_SU_ENTRY (Rodrigo) > - add check ==1 for dpcd_read call (ville) > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > CC: Puthikorn Voravootivat <puthik@chromium.org> > Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 2 +- > drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++-- > 2 files changed, 11 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 82f36dd..89c5249 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -170,6 +170,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > (mask) << 16 | (value); }) > #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) > #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0)) > +#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT) not here > > /* Engine ID */ > > @@ -4047,7 +4048,6 @@ enum { > #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 > #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4) > #define EDP_PSR2_IDLE_MASK 0xf > -#define EDP_FRAMES_BEFORE_SU_ENTRY (1<<4) move here > > #define EDP_PSR2_STATUS_CTL _MMIO(0x6f940) > #define EDP_PSR2_STATUS_STATE_MASK (0xf<<28) > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c > index 0a17d1f..e505fa6 100644 > --- a/drivers/gpu/drm/i915/intel_psr.c > +++ b/drivers/gpu/drm/i915/intel_psr.c > @@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) > */ > uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames); > uint32_t val; > + uint8_t sink_latency; > > val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT; > > @@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) > * mesh at all with our frontbuffer tracking. And the hw alone isn't > * good enough. */ > val |= EDP_PSR2_ENABLE | > - EDP_SU_TRACK_ENABLE | > - EDP_FRAMES_BEFORE_SU_ENTRY; > + EDP_SU_TRACK_ENABLE; > + > + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY, > + &sink_latency) == 1) { > + sink_latency = sink_latency & DP_MAX_RESYNC_FRAME_CNT_MASK; sink_latency &= DP_MAX_RESYNC_FRAME_CNT_MASK; with those changes Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > + } else { > + sink_latency = 0; > + } > + val |= EDP_PSR2_FRAME_BEFORE_SU(sink_latency + 1); > > if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5) > val |= EDP_PSR2_TP2_TIME_2500; > -- > 1.9.1 >
On Fri, Sep 22, 2017 at 03:58:36PM +0000, vathsala nagaraju wrote: > Set frames before SU entry value for max resync frame count of > dpcd register 2009, bit field 0:3. > > v2 : > - add macro EDP_PSR2_FRAME_BEFORE_SU (Rodrigo) > - remove EDP_FRAMES_BEFORE_SU_ENTRY (Rodrigo) > - add check ==1 for dpcd_read call (ville) > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > CC: Puthikorn Voravootivat <puthik@chromium.org> > Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com> Merged both patches to dinq. Thanks for the patches. I'm anxiously waiting the PSR2 related workaroud(s)! ;) Thanks, Rodrigo. > --- > drivers/gpu/drm/i915/i915_reg.h | 2 +- > drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++-- > 2 files changed, 11 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 82f36dd..89c5249 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -170,6 +170,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > (mask) << 16 | (value); }) > #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) > #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0)) > +#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT) > > /* Engine ID */ > > @@ -4047,7 +4048,6 @@ enum { > #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 > #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4) > #define EDP_PSR2_IDLE_MASK 0xf > -#define EDP_FRAMES_BEFORE_SU_ENTRY (1<<4) > > #define EDP_PSR2_STATUS_CTL _MMIO(0x6f940) > #define EDP_PSR2_STATUS_STATE_MASK (0xf<<28) > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c > index 0a17d1f..e505fa6 100644 > --- a/drivers/gpu/drm/i915/intel_psr.c > +++ b/drivers/gpu/drm/i915/intel_psr.c > @@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) > */ > uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames); > uint32_t val; > + uint8_t sink_latency; > > val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT; > > @@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) > * mesh at all with our frontbuffer tracking. And the hw alone isn't > * good enough. */ > val |= EDP_PSR2_ENABLE | > - EDP_SU_TRACK_ENABLE | > - EDP_FRAMES_BEFORE_SU_ENTRY; > + EDP_SU_TRACK_ENABLE; > + > + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY, > + &sink_latency) == 1) { > + sink_latency = sink_latency & DP_MAX_RESYNC_FRAME_CNT_MASK; > + } else { > + sink_latency = 0; > + } > + val |= EDP_PSR2_FRAME_BEFORE_SU(sink_latency + 1); > > if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5) > val |= EDP_PSR2_TP2_TIME_2500; > -- > 1.9.1 >
On Thu, 28 Sep 2017, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> Merged both patches to dinq. Thanks for the patches.
While patch 1 was a simple addition of a few DP macros, we need to get
ack from Dave or (preferrably non-Intel) drm-misc maintainers before
queuing non-i915 patches through drm-intel.
Dave, Sean, ack after the fact...?
The patch is [1].
BR,
Jani.
[1] http://patchwork.freedesktop.org/patch/msgid/1506419953-32605-1-git-send-email-vathsala.nagaraju@intel.com
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 82f36dd..89c5249 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -170,6 +170,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) (mask) << 16 | (value); }) #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0)) +#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT) /* Engine ID */ @@ -4047,7 +4048,6 @@ enum { #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4) #define EDP_PSR2_IDLE_MASK 0xf -#define EDP_FRAMES_BEFORE_SU_ENTRY (1<<4) #define EDP_PSR2_STATUS_CTL _MMIO(0x6f940) #define EDP_PSR2_STATUS_STATE_MASK (0xf<<28) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 0a17d1f..e505fa6 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) */ uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames); uint32_t val; + uint8_t sink_latency; val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT; @@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) * mesh at all with our frontbuffer tracking. And the hw alone isn't * good enough. */ val |= EDP_PSR2_ENABLE | - EDP_SU_TRACK_ENABLE | - EDP_FRAMES_BEFORE_SU_ENTRY; + EDP_SU_TRACK_ENABLE; + + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY, + &sink_latency) == 1) { + sink_latency = sink_latency & DP_MAX_RESYNC_FRAME_CNT_MASK; + } else { + sink_latency = 0; + } + val |= EDP_PSR2_FRAME_BEFORE_SU(sink_latency + 1); if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5) val |= EDP_PSR2_TP2_TIME_2500;
Set frames before SU entry value for max resync frame count of dpcd register 2009, bit field 0:3. v2 : - add macro EDP_PSR2_FRAME_BEFORE_SU (Rodrigo) - remove EDP_FRAMES_BEFORE_SU_ENTRY (Rodrigo) - add check ==1 for dpcd_read call (ville) Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> CC: Puthikorn Voravootivat <puthik@chromium.org> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++-- 2 files changed, 11 insertions(+), 3 deletions(-)