| Message ID | 20170923061841.6123-1-treding@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Delegated to: | Bjorn Helgaas |
| Headers | show |
On Sat, Sep 23, 2017 at 11:48 AM, Thierry Reding <thierry.reding@gmail.com> wrote: > The Tegra PCI host controller can generate configuration space accesses > with byte, word and dword granularity for devices. Only root ports can't > have their configuration space accessed in this way. > > Signed-off-by: Thierry Reding <treding@nvidia.com> > --- > drivers/pci/host/pci-tegra.c | 24 ++++++++++++++++++++++-- > 1 file changed, 22 insertions(+), 2 deletions(-) > > diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c > index 9c40da54f88a..e8e1ddbaabc9 100644 > --- a/drivers/pci/host/pci-tegra.c > +++ b/drivers/pci/host/pci-tegra.c > @@ -491,12 +491,32 @@ static void __iomem *tegra_pcie_map_bus(struct pci_bus *bus, > return addr; > } > > +static int tegra_pcie_config_read(struct pci_bus *bus, unsigned int devfn, > + int where, int size, u32 *value) > +{ > + if (bus->number == 0) > + return pci_generic_config_read32(bus, devfn, where, size, > + value); > + > + return pci_generic_config_read(bus, devfn, where, size, value); Since T20, T30 and T124 had issues with 8-bit and 16-bit end point config accesses, generic accessors should be used only for T210 > +} > + > +static int tegra_pcie_config_write(struct pci_bus *bus, unsigned int devfn, > + int where, int size, u32 value) > +{ > + if (bus->number == 0) > + return pci_generic_config_write32(bus, devfn, where, size, > + value); > + > + return pci_generic_config_write(bus, devfn, where, size, value); same as above. > +} > + > static struct pci_ops tegra_pcie_ops = { > .add_bus = tegra_pcie_add_bus, > .remove_bus = tegra_pcie_remove_bus, > .map_bus = tegra_pcie_map_bus, > - .read = pci_generic_config_read32, > - .write = pci_generic_config_write32, > + .read = tegra_pcie_config_read, > + .write = tegra_pcie_config_write, > }; > > static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port) > -- > 2.14.1 >
On Wed, Sep 27, 2017 at 02:26:04PM +0530, vidya sagar wrote: > On Sat, Sep 23, 2017 at 11:48 AM, Thierry Reding > <thierry.reding@gmail.com> wrote: > > The Tegra PCI host controller can generate configuration space accesses > > with byte, word and dword granularity for devices. Only root ports can't > > have their configuration space accessed in this way. > > > > Signed-off-by: Thierry Reding <treding@nvidia.com> > > --- > > drivers/pci/host/pci-tegra.c | 24 ++++++++++++++++++++++-- > > 1 file changed, 22 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c > > index 9c40da54f88a..e8e1ddbaabc9 100644 > > --- a/drivers/pci/host/pci-tegra.c > > +++ b/drivers/pci/host/pci-tegra.c > > @@ -491,12 +491,32 @@ static void __iomem *tegra_pcie_map_bus(struct pci_bus *bus, > > return addr; > > } > > > > +static int tegra_pcie_config_read(struct pci_bus *bus, unsigned int devfn, > > + int where, int size, u32 *value) > > +{ > > + if (bus->number == 0) > > + return pci_generic_config_read32(bus, devfn, where, size, > > + value); > > + > > + return pci_generic_config_read(bus, devfn, where, size, value); > > Since T20, T30 and T124 had issues with 8-bit and 16-bit end point > config accesses, generic accessors should be used only for T210 I thought that 8-bit and 16-bit configuration space accesses were only ever problematic for the root ports. I've certainly not seen 8-bit and 16-bit accesses fail on any of the devices I tested on. That is, this patch was tested on TrimSlice (Tegra20), Beaver (Tegra30), Jetson TK1 (Tegra124) and Jetson TX1 (Tegra210) without any issues. Thierry
[+cc vidya] On Fri, Sep 22, 2017 at 11:18:41PM -0700, Thierry Reding wrote: > The Tegra PCI host controller can generate configuration space accesses > with byte, word and dword granularity for devices. Only root ports can't > have their configuration space accessed in this way. > > Signed-off-by: Thierry Reding <treding@nvidia.com> Applied to pci/host-tegra for v4.15, thanks! > --- > drivers/pci/host/pci-tegra.c | 24 ++++++++++++++++++++++-- > 1 file changed, 22 insertions(+), 2 deletions(-) > > diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c > index 9c40da54f88a..e8e1ddbaabc9 100644 > --- a/drivers/pci/host/pci-tegra.c > +++ b/drivers/pci/host/pci-tegra.c > @@ -491,12 +491,32 @@ static void __iomem *tegra_pcie_map_bus(struct pci_bus *bus, > return addr; > } > > +static int tegra_pcie_config_read(struct pci_bus *bus, unsigned int devfn, > + int where, int size, u32 *value) > +{ > + if (bus->number == 0) > + return pci_generic_config_read32(bus, devfn, where, size, > + value); > + > + return pci_generic_config_read(bus, devfn, where, size, value); > +} > + > +static int tegra_pcie_config_write(struct pci_bus *bus, unsigned int devfn, > + int where, int size, u32 value) > +{ > + if (bus->number == 0) > + return pci_generic_config_write32(bus, devfn, where, size, > + value); > + > + return pci_generic_config_write(bus, devfn, where, size, value); > +} > + > static struct pci_ops tegra_pcie_ops = { > .add_bus = tegra_pcie_add_bus, > .remove_bus = tegra_pcie_remove_bus, > .map_bus = tegra_pcie_map_bus, > - .read = pci_generic_config_read32, > - .write = pci_generic_config_write32, > + .read = tegra_pcie_config_read, > + .write = tegra_pcie_config_write, > }; > > static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port) > -- > 2.14.1 >
diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 9c40da54f88a..e8e1ddbaabc9 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -491,12 +491,32 @@ static void __iomem *tegra_pcie_map_bus(struct pci_bus *bus, return addr; } +static int tegra_pcie_config_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *value) +{ + if (bus->number == 0) + return pci_generic_config_read32(bus, devfn, where, size, + value); + + return pci_generic_config_read(bus, devfn, where, size, value); +} + +static int tegra_pcie_config_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 value) +{ + if (bus->number == 0) + return pci_generic_config_write32(bus, devfn, where, size, + value); + + return pci_generic_config_write(bus, devfn, where, size, value); +} + static struct pci_ops tegra_pcie_ops = { .add_bus = tegra_pcie_add_bus, .remove_bus = tegra_pcie_remove_bus, .map_bus = tegra_pcie_map_bus, - .read = pci_generic_config_read32, - .write = pci_generic_config_write32, + .read = tegra_pcie_config_read, + .write = tegra_pcie_config_write, }; static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
The Tegra PCI host controller can generate configuration space accesses with byte, word and dword granularity for devices. Only root ports can't have their configuration space accessed in this way. Signed-off-by: Thierry Reding <treding@nvidia.com> --- drivers/pci/host/pci-tegra.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-)