diff mbox

[rdma-core] providers/i40iw: Do not generate CQE for RTR on QP flush

Message ID 20171008233741.9168-1-tatyana.e.nikolova@intel.com (mailing list archive)
State Accepted
Headers show

Commit Message

Nikolova, Tatyana E Oct. 8, 2017, 11:37 p.m. UTC
From: Mustafa Ismail <mustafa.ismail@intel.com>

If RTR WQE is posted and QP is flushed, a CQE is
incorrectly generated for the RTR WQE. Add code
to look for the RTR and not generate a CQE when
QP is flushed.

Signed-off-by: Mustafa Ismail <mustafa.ismail@intel.com>
Signed-off-by: Tatyana Nikolova <tatyana.e.nikolova@intel.com>
---
 providers/i40iw/i40iw_uk.c   | 12 ++++++++++++
 providers/i40iw/i40iw_user.h |  1 +
 2 files changed, 13 insertions(+)

Comments

Leon Romanovsky Oct. 9, 2017, 7:26 a.m. UTC | #1
On Sun, Oct 08, 2017 at 06:37:41PM -0500, Tatyana Nikolova wrote:
> From: Mustafa Ismail <mustafa.ismail@intel.com>
>
> If RTR WQE is posted and QP is flushed, a CQE is
> incorrectly generated for the RTR WQE. Add code
> to look for the RTR and not generate a CQE when
> QP is flushed.
>
> Signed-off-by: Mustafa Ismail <mustafa.ismail@intel.com>
> Signed-off-by: Tatyana Nikolova <tatyana.e.nikolova@intel.com>
> ---
>  providers/i40iw/i40iw_uk.c   | 12 ++++++++++++
>  providers/i40iw/i40iw_user.h |  1 +
>  2 files changed, 13 insertions(+)
>

Thanks, applied.
diff mbox

Patch

diff --git a/providers/i40iw/i40iw_uk.c b/providers/i40iw/i40iw_uk.c
index ea3255f7..4c7e5cff 100644
--- a/providers/i40iw/i40iw_uk.c
+++ b/providers/i40iw/i40iw_uk.c
@@ -829,6 +829,17 @@  static enum i40iw_status_code i40iw_cq_poll_completion(struct i40iw_cq_uk *cq,
 		I40IW_RING_SET_TAIL(qp->rq_ring, array_idx + 1);
 		pring = &qp->rq_ring;
 	} else {
+		if (qp->first_sq_wq) {
+			qp->first_sq_wq = false;
+			if (!wqe_idx && (qp->sq_ring.head == qp->sq_ring.tail)) {
+				I40IW_RING_MOVE_HEAD_NOCHECK(cq->cq_ring);
+				I40IW_RING_MOVE_TAIL(cq->cq_ring);
+				set_64bit_val(cq->shadow_area, I40IW_BYTE_0,
+					      I40IW_RING_GETCURRENT_HEAD(cq->cq_ring));
+				memset(info, 0, sizeof(struct i40iw_cq_poll_info));
+				return i40iw_cq_poll_completion(cq, info);
+			}
+		}
 
 		if (info->comp_status != I40IW_COMPL_STATUS_FLUSHED) {
 			info->wr_id = qp->sq_wrtrk_array[wqe_idx].wrid;
@@ -997,6 +1008,7 @@  enum i40iw_status_code i40iw_qp_uk_init(struct i40iw_qp_uk *qp,
 	I40IW_RING_MOVE_TAIL(qp->sq_ring);
 	I40IW_RING_MOVE_HEAD(qp->initial_ring, ret_code);
 	qp->swqe_polarity = 1;
+	qp->first_sq_wq = true;
 	qp->swqe_polarity_deferred = 1;
 	qp->rwqe_polarity = 0;
 
diff --git a/providers/i40iw/i40iw_user.h b/providers/i40iw/i40iw_user.h
index 1e95c23a..7bceca43 100644
--- a/providers/i40iw/i40iw_user.h
+++ b/providers/i40iw/i40iw_user.h
@@ -382,6 +382,7 @@  struct i40iw_qp_uk {
 	u8 rwqe_polarity;
 	u8 rq_wqe_size;
 	u8 rq_wqe_size_multiplier;
+	bool first_sq_wq;
 	bool deferred_flag;
 };