| Message ID | 20171008042906.46779-3-icenowy@aosc.io (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Sun, Oct 08, 2017 at 04:29:02AM +0000, Icenowy Zheng wrote: > From: Icenowy Zheng <icenowy@aosc.xyz> > > Allwinner R40 SoC features a USB OTG port and two USB HOST ports. > > Add support for the host ports in the DTSI file. > > The OTG controller still cannot work with existing compatibles, and needs > more investigation. So it's not added yet. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> > --- > arch/arm/boot/dts/sun8i-r40.dtsi | 78 ++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 78 insertions(+) > > diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi > index d5a6745409ae..f6c917cbbaac 100644 > --- a/arch/arm/boot/dts/sun8i-r40.dtsi > +++ b/arch/arm/boot/dts/sun8i-r40.dtsi > @@ -173,6 +173,84 @@ > #size-cells = <0>; > }; > > + usbphy: phy@1c13400 { > + compatible = "allwinner,sun8i-r40-usb-phy"; > + reg = <0x01c13400 0x14>, > + <0x01c14800 0x4>, > + <0x01c19800 0x4>, > + <0x01c1c800 0x4>; > + reg-names = "phy_ctrl", > + "pmu0", > + "pmu1", > + "pmu2"; > + clocks = <&ccu CLK_USB_PHY0>, > + <&ccu CLK_USB_PHY1>, > + <&ccu CLK_USB_PHY2>; > + clock-names = "usb0_phy", > + "usb1_phy", > + "usb2_phy"; > + resets = <&ccu RST_USB_PHY0>, > + <&ccu RST_USB_PHY1>, > + <&ccu RST_USB_PHY2>; > + reset-names = "usb0_reset", > + "usb1_reset", > + "usb2_reset"; > + status = "disabled"; > + #phy-cells = <1>; > + }; > + > + ehci1: usb@1c19000 { > + compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; > + reg = <0x01c19000 0x100>; What is the actual size here? > + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_OHCI1>, > + <&ccu CLK_BUS_EHCI1>, > + <&ccu CLK_USB_OHCI1>; > + resets = <&ccu RST_BUS_OHCI1>, > + <&ccu RST_BUS_EHCI1>; Why do you need to take the OHCI resources too? Maxime
于 2017年10月10日 GMT+08:00 上午5:03:40, Maxime Ripard <maxime.ripard@free-electrons.com> 写到: >On Sun, Oct 08, 2017 at 04:29:02AM +0000, Icenowy Zheng wrote: >> From: Icenowy Zheng <icenowy@aosc.xyz> >> >> Allwinner R40 SoC features a USB OTG port and two USB HOST ports. >> >> Add support for the host ports in the DTSI file. >> >> The OTG controller still cannot work with existing compatibles, and >needs >> more investigation. So it's not added yet. >> >> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> >> --- >> arch/arm/boot/dts/sun8i-r40.dtsi | 78 >++++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 78 insertions(+) >> >> diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi >b/arch/arm/boot/dts/sun8i-r40.dtsi >> index d5a6745409ae..f6c917cbbaac 100644 >> --- a/arch/arm/boot/dts/sun8i-r40.dtsi >> +++ b/arch/arm/boot/dts/sun8i-r40.dtsi >> @@ -173,6 +173,84 @@ >> #size-cells = <0>; >> }; >> >> + usbphy: phy@1c13400 { >> + compatible = "allwinner,sun8i-r40-usb-phy"; >> + reg = <0x01c13400 0x14>, >> + <0x01c14800 0x4>, >> + <0x01c19800 0x4>, >> + <0x01c1c800 0x4>; >> + reg-names = "phy_ctrl", >> + "pmu0", >> + "pmu1", >> + "pmu2"; >> + clocks = <&ccu CLK_USB_PHY0>, >> + <&ccu CLK_USB_PHY1>, >> + <&ccu CLK_USB_PHY2>; >> + clock-names = "usb0_phy", >> + "usb1_phy", >> + "usb2_phy"; >> + resets = <&ccu RST_USB_PHY0>, >> + <&ccu RST_USB_PHY1>, >> + <&ccu RST_USB_PHY2>; >> + reset-names = "usb0_reset", >> + "usb1_reset", >> + "usb2_reset"; >> + status = "disabled"; >> + #phy-cells = <1>; >> + }; >> + >> + ehci1: usb@1c19000 { >> + compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; >> + reg = <0x01c19000 0x100>; > >What is the actual size here? The OHCI/EHCI/PHY-PHY three parts are listed in the user manual as one MMIO zone. The size can be at most 0x400, as the OHCI is at offset 0x400. > >> + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&ccu CLK_BUS_OHCI1>, >> + <&ccu CLK_BUS_EHCI1>, >> + <&ccu CLK_USB_OHCI1>; >> + resets = <&ccu RST_BUS_OHCI1>, >> + <&ccu RST_BUS_EHCI1>; > >Why do you need to take the OHCI resources too? AW's strange design -- without OHCI resources taken EHCI won't work. > >Maxime
On Tue, Oct 10, 2017 at 07:24:28AM +0800, Icenowy Zheng wrote: > >> + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; > >> + clocks = <&ccu CLK_BUS_OHCI1>, > >> + <&ccu CLK_BUS_EHCI1>, > >> + <&ccu CLK_USB_OHCI1>; > >> + resets = <&ccu RST_BUS_OHCI1>, > >> + <&ccu RST_BUS_EHCI1>; > > > >Why do you need to take the OHCI resources too? > > AW's strange design -- without OHCI resources taken EHCI > won't work. How has this been tested? Thanks! Maxime
在 2017-10-16 17:32，Maxime Ripard 写道： > On Tue, Oct 10, 2017 at 07:24:28AM +0800, Icenowy Zheng wrote: >> >> + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; >> >> + clocks = <&ccu CLK_BUS_OHCI1>, >> >> + <&ccu CLK_BUS_EHCI1>, >> >> + <&ccu CLK_USB_OHCI1>; >> >> + resets = <&ccu RST_BUS_OHCI1>, >> >> + <&ccu RST_BUS_EHCI1>; >> > >> >Why do you need to take the OHCI resources too? >> >> AW's strange design -- without OHCI resources taken EHCI >> won't work. > > How has this been tested? As EHCI is probed before OHCI, this behavior is easy to appear if the OHCI resources are removed. > > Thanks! > Maxime > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On Mon, Oct 16, 2017 at 05:39:58PM +0800, icenowy@aosc.io wrote: > 在 2017-10-16 17:32，Maxime Ripard 写道： > > On Tue, Oct 10, 2017 at 07:24:28AM +0800, Icenowy Zheng wrote: > > > >> + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; > > > >> + clocks = <&ccu CLK_BUS_OHCI1>, > > > >> + <&ccu CLK_BUS_EHCI1>, > > > >> + <&ccu CLK_USB_OHCI1>; > > > >> + resets = <&ccu RST_BUS_OHCI1>, > > > >> + <&ccu RST_BUS_EHCI1>; > > > > > > > >Why do you need to take the OHCI resources too? > > > > > > AW's strange design -- without OHCI resources taken EHCI > > > won't work. > > > > How has this been tested? > > As EHCI is probed before OHCI, this behavior is easy to > appear if the OHCI resources are removed. And what is "this behaviour" exactly? What have you tested, what device did you connect, what is the outcome that isn't something you expected, etc. Maxime
在 2017-10-16 20:06，Maxime Ripard 写道： > On Mon, Oct 16, 2017 at 05:39:58PM +0800, icenowy@aosc.io wrote: >> 在 2017-10-16 17:32，Maxime Ripard 写道： >> > On Tue, Oct 10, 2017 at 07:24:28AM +0800, Icenowy Zheng wrote: >> > > >> + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; >> > > >> + clocks = <&ccu CLK_BUS_OHCI1>, >> > > >> + <&ccu CLK_BUS_EHCI1>, >> > > >> + <&ccu CLK_USB_OHCI1>; >> > > >> + resets = <&ccu RST_BUS_OHCI1>, >> > > >> + <&ccu RST_BUS_EHCI1>; >> > > > >> > > >Why do you need to take the OHCI resources too? >> > > >> > > AW's strange design -- without OHCI resources taken EHCI >> > > won't work. >> > >> > How has this been tested? >> >> As EHCI is probed before OHCI, this behavior is easy to >> appear if the OHCI resources are removed. > > And what is "this behaviour" exactly? > > What have you tested, what device did you connect, what is the outcome > that isn't something you expected, etc. Oh sorry this weird behavior doesn't exist on R40, although it do exist on H3/H5/A64. I will fix this in the next version. > > Maxime
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index d5a6745409ae..f6c917cbbaac 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -173,6 +173,84 @@ #size-cells = <0>; }; + usbphy: phy@1c13400 { + compatible = "allwinner,sun8i-r40-usb-phy"; + reg = <0x01c13400 0x14>, + <0x01c14800 0x4>, + <0x01c19800 0x4>, + <0x01c1c800 0x4>; + reg-names = "phy_ctrl", + "pmu0", + "pmu1", + "pmu2"; + clocks = <&ccu CLK_USB_PHY0>, + <&ccu CLK_USB_PHY1>, + <&ccu CLK_USB_PHY2>; + clock-names = "usb0_phy", + "usb1_phy", + "usb2_phy"; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>, + <&ccu RST_USB_PHY2>; + reset-names = "usb0_reset", + "usb1_reset", + "usb2_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + + ehci1: usb@1c19000 { + compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; + reg = <0x01c19000 0x100>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_OHCI1>, + <&ccu CLK_BUS_EHCI1>, + <&ccu CLK_USB_OHCI1>; + resets = <&ccu RST_BUS_OHCI1>, + <&ccu RST_BUS_EHCI1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci1: usb@1c19400 { + compatible = "allwinner,sun8i-r40-ohci", "generic-ohci"; + reg = <0x01c19400 0x100>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_OHCI1>, + <&ccu CLK_USB_OHCI1>; + resets = <&ccu RST_BUS_OHCI1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci2: usb@1c1c000 { + compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; + reg = <0x01c1c000 0x100>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_OHCI2>, + <&ccu CLK_BUS_EHCI2>, + <&ccu CLK_USB_OHCI2>; + resets = <&ccu RST_BUS_OHCI2>, + <&ccu RST_BUS_EHCI2>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci2: usb@1c1c400 { + compatible = "allwinner,sun8i-r40-ohci", "generic-ohci"; + reg = <0x01c1c400 0x100>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_OHCI2>, + <&ccu CLK_USB_OHCI2>; + resets = <&ccu RST_BUS_OHCI2>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + ccu: clock@1c20000 { compatible = "allwinner,sun8i-r40-ccu"; reg = <0x01c20000 0x400>;