diff mbox

[v2,2/5] target/openrisc: Make coreid and numcores variable

Message ID 20171013134930.32547-3-shorne@gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

Stafford Horne Oct. 13, 2017, 1:49 p.m. UTC 
Previously coreid and numcores were hard coded as 0 and 1 respectively
as OpenRISC QEMU did not have multicore support.

Multicore support is now being added so these registers need to have
configured values.

Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 target/openrisc/sys_helper.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

Comments

Richard Henderson Oct. 13, 2017, 1:58 p.m. UTC | #1 
On 10/13/2017 06:49 AM, Stafford Horne wrote:
> Previously coreid and numcores were hard coded as 0 and 1 respectively
> as OpenRISC QEMU did not have multicore support.
> 
> Multicore support is now being added so these registers need to have
> configured values.
> 
> Signed-off-by: Stafford Horne <shorne@gmail.com>
> ---
>  target/openrisc/sys_helper.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~
Stafford Horne Oct. 13, 2017, 2:31 p.m. UTC | #2 
On Fri, Oct 13, 2017 at 06:58:21AM -0700, Richard Henderson wrote:
> On 10/13/2017 06:49 AM, Stafford Horne wrote:
> > Previously coreid and numcores were hard coded as 0 and 1 respectively
> > as OpenRISC QEMU did not have multicore support.
> > 
> > Multicore support is now being added so these registers need to have
> > configured values.
> > 
> > Signed-off-by: Stafford Horne <shorne@gmail.com>
> > ---
> >  target/openrisc/sys_helper.c | 5 +++--
> >  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> 
> 
> r~

Thank you for the review.

-Stafford
diff mbox

Patch

diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index abdef5d6a5..dc6e5cc7f2 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -23,6 +23,7 @@ 
 #include "exec/exec-all.h"
 #include "exec/helper-proto.h"
 #include "exception.h"
+#include "sysemu/sysemu.h"
 
 #define TO_SPR(group, number) (((group) << 11) + (number))
 
@@ -249,10 +250,10 @@  target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
         return env->esr;
 
     case TO_SPR(0, 128): /* COREID */
-        return 0;
+        return cpu->parent_obj.cpu_index;
 
     case TO_SPR(0, 129): /* NUMCORES */
-        return 1;
+        return max_cpus;
 
     case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */
         idx = (spr - 1024);