| Message ID | 20171015232337.z3vj7ut2vpwravry@lenoch (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki On 16/10/17 02:23, Ladislav Michl wrote: > Remove now dead code. > > Signed-off-by: Ladislav Michl <ladis@linux-mips.org> > --- > arch/arm/mach-omap2/Makefile | 3 - > arch/arm/mach-omap2/gpmc-onenand.c | 349 ------------------------ > include/linux/platform_data/mtd-onenand-omap2.h | 34 --- > 3 files changed, 386 deletions(-) Since we're aiming to get rid of mach-omap2/gpmc-onenand.c I don't think we should need patches 1 to 6 that try to clean it up. Also, since nand and mach-omap2 patches would go in separate trees during the merge window, I wouldn't yet git rid of mach-omap2/gpmc-onenand.c and platform data yet. We can do that once the onenand DT adaptation is complete. > > diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile > index b3b3b3a19183..bbf22e298cb0 100644 > --- a/arch/arm/mach-omap2/Makefile > +++ b/arch/arm/mach-omap2/Makefile > @@ -234,6 +234,3 @@ obj-y += $(omap-hsmmc-m) $(omap-hsmmc-y) > obj-y += omap_phy_internal.o > > obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o > - > -onenand-$(CONFIG_MTD_ONENAND_OMAP2) := gpmc-onenand.o > -obj-y += $(onenand-m) $(onenand-y) > diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c > deleted file mode 100644 > index 2b28cc95dda4..000000000000 > --- a/arch/arm/mach-omap2/gpmc-onenand.c > +++ /dev/null > @@ -1,349 +0,0 @@ > -/* > - * linux/arch/arm/mach-omap2/gpmc-onenand.c > - * > - * Copyright (C) 2006 - 2009 Nokia Corporation > - * Contacts: Juha Yrjola > - * Tony Lindgren > - * > - * This program is free software; you can redistribute it and/or modify > - * it under the terms of the GNU General Public License version 2 as > - * published by the Free Software Foundation. > - */ > - > -#include <linux/string.h> > -#include <linux/kernel.h> > -#include <linux/platform_device.h> > -#include <linux/mtd/onenand_regs.h> > -#include <linux/io.h> > -#include <linux/omap-gpmc.h> > -#include <linux/platform_data/mtd-onenand-omap2.h> > -#include <linux/err.h> > - > -#include <asm/mach/flash.h> > - > -#include "soc.h" > - > -#define ONENAND_IO_SIZE SZ_128K > - > -static struct omap_onenand_platform_data *gpmc_onenand_data; > - > -static struct resource gpmc_onenand_resource = { > - .flags = IORESOURCE_MEM, > -}; > - > -static struct platform_device gpmc_onenand_device = { > - .name = "omap2-onenand", > - .id = -1, > - .num_resources = 1, > - .resource = &gpmc_onenand_resource, > -}; > - > -static void omap2_onenand_calc_async_timings(struct gpmc_timings *t, > - struct gpmc_settings *s) > -{ > - struct gpmc_device_timings dev_t; > - const int t_cer = 15; > - const int t_avdp = 12; > - const int t_aavdh = 7; > - const int t_ce = 76; > - const int t_aa = 76; > - const int t_oe = 20; > - const int t_cez = 20; /* max of t_cez, t_oez */ > - const int t_wpl = 40; > - const int t_wph = 30; > - > - memset(&dev_t, 0, sizeof(dev_t)); > - > - dev_t.t_avdp_r = max_t(int, t_avdp, t_cer) * 1000; > - dev_t.t_avdp_w = dev_t.t_avdp_r; > - dev_t.t_aavdh = t_aavdh * 1000; > - dev_t.t_aa = t_aa * 1000; > - dev_t.t_ce = t_ce * 1000; > - dev_t.t_oe = t_oe * 1000; > - dev_t.t_cez_r = t_cez * 1000; > - dev_t.t_cez_w = dev_t.t_cez_r; > - dev_t.t_wpl = t_wpl * 1000; > - dev_t.t_wph = t_wph * 1000; > - > - gpmc_calc_timings(t, s, &dev_t); > -} > - > -static void omap2_onenand_set_async_mode(void __iomem *onenand_base) > -{ > - u32 reg; > - > - /* Ensure sync read and sync write are disabled */ > - reg = readw(onenand_base + ONENAND_REG_SYS_CFG1); > - reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE; > - writew(reg, onenand_base + ONENAND_REG_SYS_CFG1); > -} > - > -static void set_onenand_cfg(void __iomem *onenand_base, > - bool sr, bool sw, int latency) > -{ > - u32 reg = ONENAND_SYS_CFG1_RDY | ONENAND_SYS_CFG1_INT; > - > - reg |= (latency << ONENAND_SYS_CFG1_BRL_SHIFT) | > - ONENAND_SYS_CFG1_BL_16; > - if (latency > 5) > - reg |= ONENAND_SYS_CFG1_HF; > - if (latency > 7) > - reg |= ONENAND_SYS_CFG1_VHF; > - if (sr) > - reg |= ONENAND_SYS_CFG1_SYNC_READ; > - if (sw) > - reg |= ONENAND_SYS_CFG1_SYNC_WRITE; > - > - writew(reg, onenand_base + ONENAND_REG_SYS_CFG1); > -} > - > -static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg, > - void __iomem *onenand_base) > -{ > - u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID); > - int freq; > - > - switch ((ver >> 4) & 0xf) { > - case 0: > - freq = 40; > - break; > - case 1: > - freq = 54; > - break; > - case 2: > - freq = 66; > - break; > - case 3: > - freq = 83; > - break; > - case 4: > - freq = 104; > - break; > - default: > - pr_err("onenand rate not detected, bad GPMC async timings?\n"); > - freq = 0; > - } > - > - return freq; > -} > - > -static int omap2_onenand_calc_sync_timings(struct gpmc_timings *t, > - struct gpmc_settings *s, > - int freq) > -{ > - struct gpmc_device_timings dev_t; > - const int t_cer = 15; > - const int t_avdp = 12; > - const int t_cez = 20; /* max of t_cez, t_oez */ > - const int t_wpl = 40; > - const int t_wph = 30; > - int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo; > - int div, gpmc_clk_ns, latency; > - > - if (!s->sync_read && !s->sync_write) > - return 0; > - > - switch (freq) { > - case 104: > - min_gpmc_clk_period = 9600; /* 104 MHz */ > - t_ces = 3; > - t_avds = 4; > - t_avdh = 2; > - t_ach = 3; > - t_aavdh = 6; > - t_rdyo = 6; > - break; > - case 83: > - min_gpmc_clk_period = 12000; /* 83 MHz */ > - t_ces = 5; > - t_avds = 4; > - t_avdh = 2; > - t_ach = 6; > - t_aavdh = 6; > - t_rdyo = 9; > - break; > - case 66: > - min_gpmc_clk_period = 15000; /* 66 MHz */ > - t_ces = 6; > - t_avds = 5; > - t_avdh = 2; > - t_ach = 6; > - t_aavdh = 6; > - t_rdyo = 11; > - break; > - default: > - min_gpmc_clk_period = 18500; /* 54 MHz */ > - t_ces = 7; > - t_avds = 7; > - t_avdh = 7; > - t_ach = 9; > - t_aavdh = 7; > - t_rdyo = 15; > - s->sync_write = false; > - s->burst_write = false; > - break; > - } > - > - div = gpmc_calc_divider(min_gpmc_clk_period); > - gpmc_clk_ns = gpmc_ticks_to_ns(div); > - if (gpmc_clk_ns < 12) /* >83 MHz */ > - latency = 8; > - else if (gpmc_clk_ns < 15) /* >66 MHz */ > - latency = 6; > - else if (gpmc_clk_ns >= 25) /* 40 MHz */ > - latency = 3; > - else > - latency = 4; > - > - /* Set synchronous read timings */ > - memset(&dev_t, 0, sizeof(dev_t)); > - > - if (!s->sync_write) { > - dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000; > - dev_t.t_wpl = t_wpl * 1000; > - dev_t.t_wph = t_wph * 1000; > - dev_t.t_aavdh = t_aavdh * 1000; > - } > - dev_t.ce_xdelay = true; > - dev_t.avd_xdelay = true; > - dev_t.oe_xdelay = true; > - dev_t.we_xdelay = true; > - dev_t.clk = min_gpmc_clk_period; > - dev_t.t_bacc = dev_t.clk; > - dev_t.t_ces = t_ces * 1000; > - dev_t.t_avds = t_avds * 1000; > - dev_t.t_avdh = t_avdh * 1000; > - dev_t.t_ach = t_ach * 1000; > - dev_t.cyc_iaa = (latency + 1); > - dev_t.t_cez_r = t_cez * 1000; > - dev_t.t_cez_w = dev_t.t_cez_r; > - dev_t.cyc_aavdh_oe = 1; > - dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period; > - > - gpmc_calc_timings(t, s, &dev_t); > - > - return latency; > -} > - > -static int omap2_onenand_setup_async(void __iomem *onenand_base) > -{ > - struct gpmc_timings t; > - struct gpmc_settings s; > - int ret; > - > - /* > - * Note that we need to keep sync_write set for the call to > - * omap2_onenand_set_async_mode() to work to detect the onenand > - * supported clock rate for the sync timings. > - */ > - gpmc_read_settings_dt(gpmc_onenand_data->of_node, &s); > - s.sync_read = false; > - s.sync_write = true; > - > - omap2_onenand_calc_async_timings(&t, &s); > - > - ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &s); > - if (ret < 0) > - return ret; > - > - ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t, &s); > - if (ret < 0) > - return ret; > - > - omap2_onenand_set_async_mode(onenand_base); > - > - return 0; > -} > - > -static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr) > -{ > - int ret, latency, freq = *freq_ptr; > - struct gpmc_timings t; > - struct gpmc_settings s; > - > - if (!freq) { > - /* Very first call freq is not known */ > - freq = omap2_onenand_get_freq(gpmc_onenand_data, onenand_base); > - if (!freq) > - return -ENODEV; > - } > - > - gpmc_read_settings_dt(gpmc_onenand_data->of_node, &s); > - > - latency = omap2_onenand_calc_sync_timings(&t, &s, freq); > - if (latency > 0) { > - ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &s); > - if (ret < 0) > - return ret; > - > - ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t, &s); > - if (ret < 0) > - return ret; > - > - set_onenand_cfg(onenand_base, s.sync_read, s.sync_write, > - latency); > - } > - > - *freq_ptr = freq; > - > - return 0; > -} > - > -static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr) > -{ > - struct device *dev = &gpmc_onenand_device.dev; > - int ret; > - > - ret = omap2_onenand_setup_async(onenand_base); > - if (ret) { > - dev_err(dev, "unable to set to async mode\n"); > - return ret; > - } > - > - ret = omap2_onenand_setup_sync(onenand_base, freq_ptr); > - if (ret) > - dev_err(dev, "unable to set to sync mode\n"); > - return ret; > -} > - > -int gpmc_omap_onenand_init(struct omap_onenand_platform_data *_onenand_data) > -{ > - gpmc_onenand_data = _onenand_data; > - gpmc_onenand_data->onenand_setup = gpmc_onenand_setup; > - gpmc_onenand_device.dev.platform_data = gpmc_onenand_data; > - > - if (cpu_is_omap34xx()) > - gpmc_onenand_data->flags |= ONENAND_IN_OMAP34XX; > - else > - gpmc_onenand_data->flags &= ~ONENAND_IN_OMAP34XX; > - > - return 0; > - > -} > - > -int gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data) > -{ > - int err; > - struct device *dev = &gpmc_onenand_device.dev; > - > - gpmc_omap_onenand_init(_onenand_data); > - > - err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE, > - (unsigned long *)&gpmc_onenand_resource.start); > - if (err < 0) { > - dev_err(dev, "Cannot request GPMC CS %d, error %d\n", > - gpmc_onenand_data->cs, err); > - return err; > - } > - > - gpmc_onenand_resource.end = gpmc_onenand_resource.start + > - ONENAND_IO_SIZE - 1; > - > - err = platform_device_register(&gpmc_onenand_device); > - if (err) { > - dev_err(dev, "Unable to register OneNAND device\n"); > - gpmc_cs_free(gpmc_onenand_data->cs); > - } > - > - return err; > -} > diff --git a/include/linux/platform_data/mtd-onenand-omap2.h b/include/linux/platform_data/mtd-onenand-omap2.h > deleted file mode 100644 > index 56ff0e6f5ad1..000000000000 > --- a/include/linux/platform_data/mtd-onenand-omap2.h > +++ /dev/null > @@ -1,34 +0,0 @@ > -/* > - * Copyright (C) 2006 Nokia Corporation > - * Author: Juha Yrjola > - * > - * This program is free software; you can redistribute it and/or modify > - * it under the terms of the GNU General Public License version 2 as > - * published by the Free Software Foundation. > - */ > - > -#ifndef __MTD_ONENAND_OMAP2_H > -#define __MTD_ONENAND_OMAP2_H > - > -#include <linux/mtd/mtd.h> > -#include <linux/mtd/partitions.h> > - > -#define ONENAND_SYNC_READ (1 << 0) > -#define ONENAND_SYNC_READWRITE (1 << 1) > -#define ONENAND_IN_OMAP34XX (1 << 2) > - > -struct omap_onenand_platform_data { > - int cs; > - int gpio_irq; > - struct mtd_partition *parts; > - int nr_parts; > - int (*onenand_setup)(void __iomem *, int *freq_ptr); > - int dma_channel; > - u8 flags; > - u8 regulator_can_sleep; > - u8 skip_initial_unlocking; > - > - /* for passing the partitions */ > - struct device_node *of_node; > -}; > -#endif >
On Tue, Oct 17, 2017 at 11:11:41AM +0300, Roger Quadros wrote: > > Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki > > On 16/10/17 02:23, Ladislav Michl wrote: > > Remove now dead code. > > > > Signed-off-by: Ladislav Michl <ladis@linux-mips.org> > > --- > > arch/arm/mach-omap2/Makefile | 3 - > > arch/arm/mach-omap2/gpmc-onenand.c | 349 ------------------------ > > include/linux/platform_data/mtd-onenand-omap2.h | 34 --- > > 3 files changed, 386 deletions(-) > > Since we're aiming to get rid of mach-omap2/gpmc-onenand.c I don't think > we should need patches 1 to 6 that try to clean it up. As stated in cover letter, sole purpose of patches 1-5 is to get functions which are later moved into drivers/memory/omap-gpmc.c. I hope someone will volunteer to review them and verify reasoning. Once agreed modifications are correct, I'll drop them from next version. On the other side, it is always nice when you know where code comes from frm the git history. > Also, since nand and mach-omap2 patches would go in separate trees during the merge window, > I wouldn't yet git rid of mach-omap2/gpmc-onenand.c and platform data yet. > We can do that once the onenand DT adaptation is complete. Sure. Idea was to merge patches 6,7 and 8 via linux-omap and then patch 9 via linux-mtd. I do not think it is possible merge everything in paralel during one merge window. Clean uu can be then done anytime later. > > diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile > > index b3b3b3a19183..bbf22e298cb0 100644 > > --- a/arch/arm/mach-omap2/Makefile > > +++ b/arch/arm/mach-omap2/Makefile > > @@ -234,6 +234,3 @@ obj-y += $(omap-hsmmc-m) $(omap-hsmmc-y) > > obj-y += omap_phy_internal.o > > > > obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o > > - > > -onenand-$(CONFIG_MTD_ONENAND_OMAP2) := gpmc-onenand.o > > -obj-y += $(onenand-m) $(onenand-y) > > diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c > > deleted file mode 100644 > > index 2b28cc95dda4..000000000000 > > --- a/arch/arm/mach-omap2/gpmc-onenand.c > > +++ /dev/null > > @@ -1,349 +0,0 @@ > > -/* > > - * linux/arch/arm/mach-omap2/gpmc-onenand.c > > - * > > - * Copyright (C) 2006 - 2009 Nokia Corporation > > - * Contacts: Juha Yrjola > > - * Tony Lindgren > > - * > > - * This program is free software; you can redistribute it and/or modify > > - * it under the terms of the GNU General Public License version 2 as > > - * published by the Free Software Foundation. > > - */ > > - > > -#include <linux/string.h> > > -#include <linux/kernel.h> > > -#include <linux/platform_device.h> > > -#include <linux/mtd/onenand_regs.h> > > -#include <linux/io.h> > > -#include <linux/omap-gpmc.h> > > -#include <linux/platform_data/mtd-onenand-omap2.h> > > -#include <linux/err.h> > > - > > -#include <asm/mach/flash.h> > > - > > -#include "soc.h" > > - > > -#define ONENAND_IO_SIZE SZ_128K > > - > > -static struct omap_onenand_platform_data *gpmc_onenand_data; > > - > > -static struct resource gpmc_onenand_resource = { > > - .flags = IORESOURCE_MEM, > > -}; > > - > > -static struct platform_device gpmc_onenand_device = { > > - .name = "omap2-onenand", > > - .id = -1, > > - .num_resources = 1, > > - .resource = &gpmc_onenand_resource, > > -}; > > - > > -static void omap2_onenand_calc_async_timings(struct gpmc_timings *t, > > - struct gpmc_settings *s) > > -{ > > - struct gpmc_device_timings dev_t; > > - const int t_cer = 15; > > - const int t_avdp = 12; > > - const int t_aavdh = 7; > > - const int t_ce = 76; > > - const int t_aa = 76; > > - const int t_oe = 20; > > - const int t_cez = 20; /* max of t_cez, t_oez */ > > - const int t_wpl = 40; > > - const int t_wph = 30; > > - > > - memset(&dev_t, 0, sizeof(dev_t)); > > - > > - dev_t.t_avdp_r = max_t(int, t_avdp, t_cer) * 1000; > > - dev_t.t_avdp_w = dev_t.t_avdp_r; > > - dev_t.t_aavdh = t_aavdh * 1000; > > - dev_t.t_aa = t_aa * 1000; > > - dev_t.t_ce = t_ce * 1000; > > - dev_t.t_oe = t_oe * 1000; > > - dev_t.t_cez_r = t_cez * 1000; > > - dev_t.t_cez_w = dev_t.t_cez_r; > > - dev_t.t_wpl = t_wpl * 1000; > > - dev_t.t_wph = t_wph * 1000; > > - > > - gpmc_calc_timings(t, s, &dev_t); > > -} > > - > > -static void omap2_onenand_set_async_mode(void __iomem *onenand_base) > > -{ > > - u32 reg; > > - > > - /* Ensure sync read and sync write are disabled */ > > - reg = readw(onenand_base + ONENAND_REG_SYS_CFG1); > > - reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE; > > - writew(reg, onenand_base + ONENAND_REG_SYS_CFG1); > > -} > > - > > -static void set_onenand_cfg(void __iomem *onenand_base, > > - bool sr, bool sw, int latency) > > -{ > > - u32 reg = ONENAND_SYS_CFG1_RDY | ONENAND_SYS_CFG1_INT; > > - > > - reg |= (latency << ONENAND_SYS_CFG1_BRL_SHIFT) | > > - ONENAND_SYS_CFG1_BL_16; > > - if (latency > 5) > > - reg |= ONENAND_SYS_CFG1_HF; > > - if (latency > 7) > > - reg |= ONENAND_SYS_CFG1_VHF; > > - if (sr) > > - reg |= ONENAND_SYS_CFG1_SYNC_READ; > > - if (sw) > > - reg |= ONENAND_SYS_CFG1_SYNC_WRITE; > > - > > - writew(reg, onenand_base + ONENAND_REG_SYS_CFG1); > > -} > > - > > -static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg, > > - void __iomem *onenand_base) > > -{ > > - u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID); > > - int freq; > > - > > - switch ((ver >> 4) & 0xf) { > > - case 0: > > - freq = 40; > > - break; > > - case 1: > > - freq = 54; > > - break; > > - case 2: > > - freq = 66; > > - break; > > - case 3: > > - freq = 83; > > - break; > > - case 4: > > - freq = 104; > > - break; > > - default: > > - pr_err("onenand rate not detected, bad GPMC async timings?\n"); > > - freq = 0; > > - } > > - > > - return freq; > > -} > > - > > -static int omap2_onenand_calc_sync_timings(struct gpmc_timings *t, > > - struct gpmc_settings *s, > > - int freq) > > -{ > > - struct gpmc_device_timings dev_t; > > - const int t_cer = 15; > > - const int t_avdp = 12; > > - const int t_cez = 20; /* max of t_cez, t_oez */ > > - const int t_wpl = 40; > > - const int t_wph = 30; > > - int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo; > > - int div, gpmc_clk_ns, latency; > > - > > - if (!s->sync_read && !s->sync_write) > > - return 0; > > - > > - switch (freq) { > > - case 104: > > - min_gpmc_clk_period = 9600; /* 104 MHz */ > > - t_ces = 3; > > - t_avds = 4; > > - t_avdh = 2; > > - t_ach = 3; > > - t_aavdh = 6; > > - t_rdyo = 6; > > - break; > > - case 83: > > - min_gpmc_clk_period = 12000; /* 83 MHz */ > > - t_ces = 5; > > - t_avds = 4; > > - t_avdh = 2; > > - t_ach = 6; > > - t_aavdh = 6; > > - t_rdyo = 9; > > - break; > > - case 66: > > - min_gpmc_clk_period = 15000; /* 66 MHz */ > > - t_ces = 6; > > - t_avds = 5; > > - t_avdh = 2; > > - t_ach = 6; > > - t_aavdh = 6; > > - t_rdyo = 11; > > - break; > > - default: > > - min_gpmc_clk_period = 18500; /* 54 MHz */ > > - t_ces = 7; > > - t_avds = 7; > > - t_avdh = 7; > > - t_ach = 9; > > - t_aavdh = 7; > > - t_rdyo = 15; > > - s->sync_write = false; > > - s->burst_write = false; > > - break; > > - } > > - > > - div = gpmc_calc_divider(min_gpmc_clk_period); > > - gpmc_clk_ns = gpmc_ticks_to_ns(div); > > - if (gpmc_clk_ns < 12) /* >83 MHz */ > > - latency = 8; > > - else if (gpmc_clk_ns < 15) /* >66 MHz */ > > - latency = 6; > > - else if (gpmc_clk_ns >= 25) /* 40 MHz */ > > - latency = 3; > > - else > > - latency = 4; > > - > > - /* Set synchronous read timings */ > > - memset(&dev_t, 0, sizeof(dev_t)); > > - > > - if (!s->sync_write) { > > - dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000; > > - dev_t.t_wpl = t_wpl * 1000; > > - dev_t.t_wph = t_wph * 1000; > > - dev_t.t_aavdh = t_aavdh * 1000; > > - } > > - dev_t.ce_xdelay = true; > > - dev_t.avd_xdelay = true; > > - dev_t.oe_xdelay = true; > > - dev_t.we_xdelay = true; > > - dev_t.clk = min_gpmc_clk_period; > > - dev_t.t_bacc = dev_t.clk; > > - dev_t.t_ces = t_ces * 1000; > > - dev_t.t_avds = t_avds * 1000; > > - dev_t.t_avdh = t_avdh * 1000; > > - dev_t.t_ach = t_ach * 1000; > > - dev_t.cyc_iaa = (latency + 1); > > - dev_t.t_cez_r = t_cez * 1000; > > - dev_t.t_cez_w = dev_t.t_cez_r; > > - dev_t.cyc_aavdh_oe = 1; > > - dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period; > > - > > - gpmc_calc_timings(t, s, &dev_t); > > - > > - return latency; > > -} > > - > > -static int omap2_onenand_setup_async(void __iomem *onenand_base) > > -{ > > - struct gpmc_timings t; > > - struct gpmc_settings s; > > - int ret; > > - > > - /* > > - * Note that we need to keep sync_write set for the call to > > - * omap2_onenand_set_async_mode() to work to detect the onenand > > - * supported clock rate for the sync timings. > > - */ > > - gpmc_read_settings_dt(gpmc_onenand_data->of_node, &s); > > - s.sync_read = false; > > - s.sync_write = true; > > - > > - omap2_onenand_calc_async_timings(&t, &s); > > - > > - ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &s); > > - if (ret < 0) > > - return ret; > > - > > - ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t, &s); > > - if (ret < 0) > > - return ret; > > - > > - omap2_onenand_set_async_mode(onenand_base); > > - > > - return 0; > > -} > > - > > -static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr) > > -{ > > - int ret, latency, freq = *freq_ptr; > > - struct gpmc_timings t; > > - struct gpmc_settings s; > > - > > - if (!freq) { > > - /* Very first call freq is not known */ > > - freq = omap2_onenand_get_freq(gpmc_onenand_data, onenand_base); > > - if (!freq) > > - return -ENODEV; > > - } > > - > > - gpmc_read_settings_dt(gpmc_onenand_data->of_node, &s); > > - > > - latency = omap2_onenand_calc_sync_timings(&t, &s, freq); > > - if (latency > 0) { > > - ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &s); > > - if (ret < 0) > > - return ret; > > - > > - ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t, &s); > > - if (ret < 0) > > - return ret; > > - > > - set_onenand_cfg(onenand_base, s.sync_read, s.sync_write, > > - latency); > > - } > > - > > - *freq_ptr = freq; > > - > > - return 0; > > -} > > - > > -static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr) > > -{ > > - struct device *dev = &gpmc_onenand_device.dev; > > - int ret; > > - > > - ret = omap2_onenand_setup_async(onenand_base); > > - if (ret) { > > - dev_err(dev, "unable to set to async mode\n"); > > - return ret; > > - } > > - > > - ret = omap2_onenand_setup_sync(onenand_base, freq_ptr); > > - if (ret) > > - dev_err(dev, "unable to set to sync mode\n"); > > - return ret; > > -} > > - > > -int gpmc_omap_onenand_init(struct omap_onenand_platform_data *_onenand_data) > > -{ > > - gpmc_onenand_data = _onenand_data; > > - gpmc_onenand_data->onenand_setup = gpmc_onenand_setup; > > - gpmc_onenand_device.dev.platform_data = gpmc_onenand_data; > > - > > - if (cpu_is_omap34xx()) > > - gpmc_onenand_data->flags |= ONENAND_IN_OMAP34XX; > > - else > > - gpmc_onenand_data->flags &= ~ONENAND_IN_OMAP34XX; > > - > > - return 0; > > - > > -} > > - > > -int gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data) > > -{ > > - int err; > > - struct device *dev = &gpmc_onenand_device.dev; > > - > > - gpmc_omap_onenand_init(_onenand_data); > > - > > - err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE, > > - (unsigned long *)&gpmc_onenand_resource.start); > > - if (err < 0) { > > - dev_err(dev, "Cannot request GPMC CS %d, error %d\n", > > - gpmc_onenand_data->cs, err); > > - return err; > > - } > > - > > - gpmc_onenand_resource.end = gpmc_onenand_resource.start + > > - ONENAND_IO_SIZE - 1; > > - > > - err = platform_device_register(&gpmc_onenand_device); > > - if (err) { > > - dev_err(dev, "Unable to register OneNAND device\n"); > > - gpmc_cs_free(gpmc_onenand_data->cs); > > - } > > - > > - return err; > > -} > > diff --git a/include/linux/platform_data/mtd-onenand-omap2.h b/include/linux/platform_data/mtd-onenand-omap2.h > > deleted file mode 100644 > > index 56ff0e6f5ad1..000000000000 > > --- a/include/linux/platform_data/mtd-onenand-omap2.h > > +++ /dev/null > > @@ -1,34 +0,0 @@ > > -/* > > - * Copyright (C) 2006 Nokia Corporation > > - * Author: Juha Yrjola > > - * > > - * This program is free software; you can redistribute it and/or modify > > - * it under the terms of the GNU General Public License version 2 as > > - * published by the Free Software Foundation. > > - */ > > - > > -#ifndef __MTD_ONENAND_OMAP2_H > > -#define __MTD_ONENAND_OMAP2_H > > - > > -#include <linux/mtd/mtd.h> > > -#include <linux/mtd/partitions.h> > > - > > -#define ONENAND_SYNC_READ (1 << 0) > > -#define ONENAND_SYNC_READWRITE (1 << 1) > > -#define ONENAND_IN_OMAP34XX (1 << 2) > > - > > -struct omap_onenand_platform_data { > > - int cs; > > - int gpio_irq; > > - struct mtd_partition *parts; > > - int nr_parts; > > - int (*onenand_setup)(void __iomem *, int *freq_ptr); > > - int dma_channel; > > - u8 flags; > > - u8 regulator_can_sleep; > > - u8 skip_initial_unlocking; > > - > > - /* for passing the partitions */ > > - struct device_node *of_node; > > -}; > > -#endif > > > > -- > cheers, > -roger -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
* Ladislav Michl <ladis@linux-mips.org> [171017 01:51]: > On Tue, Oct 17, 2017 at 11:11:41AM +0300, Roger Quadros wrote: > > > > Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki > > > > On 16/10/17 02:23, Ladislav Michl wrote: > > > Remove now dead code. > > > > > > Signed-off-by: Ladislav Michl <ladis@linux-mips.org> > > > --- > > > arch/arm/mach-omap2/Makefile | 3 - > > > arch/arm/mach-omap2/gpmc-onenand.c | 349 ------------------------ > > > include/linux/platform_data/mtd-onenand-omap2.h | 34 --- > > > 3 files changed, 386 deletions(-) > > > > Since we're aiming to get rid of mach-omap2/gpmc-onenand.c I don't think > > we should need patches 1 to 6 that try to clean it up. > > As stated in cover letter, sole purpose of patches 1-5 is to get functions > which are later moved into drivers/memory/omap-gpmc.c. I hope someone will > volunteer to review them and verify reasoning. Once agreed modifications are > correct, I'll drop them from next version. On the other side, it is always > nice when you know where code comes from frm the git history. > > > Also, since nand and mach-omap2 patches would go in separate trees during the merge window, > > I wouldn't yet git rid of mach-omap2/gpmc-onenand.c and platform data yet. > > We can do that once the onenand DT adaptation is complete. > > Sure. Idea was to merge patches 6,7 and 8 via linux-omap and then patch 9 > via linux-mtd. I do not think it is possible merge everything in paralel > during one merge window. Clean uu can be then done anytime later. Best to merge it all via MTD, I can ack the mach-omap2 patches as needed. I also need to test at some point that onenand still works with n8x0 and n900. Regards, Tony -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index b3b3b3a19183..bbf22e298cb0 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -234,6 +234,3 @@ obj-y += $(omap-hsmmc-m) $(omap-hsmmc-y) obj-y += omap_phy_internal.o obj-$(CONFIG_MACH_OMAP2_TUSB6010) += usb-tusb6010.o - -onenand-$(CONFIG_MTD_ONENAND_OMAP2) := gpmc-onenand.o -obj-y += $(onenand-m) $(onenand-y) diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c deleted file mode 100644 index 2b28cc95dda4..000000000000 --- a/arch/arm/mach-omap2/gpmc-onenand.c +++ /dev/null @@ -1,349 +0,0 @@ -/* - * linux/arch/arm/mach-omap2/gpmc-onenand.c - * - * Copyright (C) 2006 - 2009 Nokia Corporation - * Contacts: Juha Yrjola - * Tony Lindgren - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/string.h> -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/mtd/onenand_regs.h> -#include <linux/io.h> -#include <linux/omap-gpmc.h> -#include <linux/platform_data/mtd-onenand-omap2.h> -#include <linux/err.h> - -#include <asm/mach/flash.h> - -#include "soc.h" - -#define ONENAND_IO_SIZE SZ_128K - -static struct omap_onenand_platform_data *gpmc_onenand_data; - -static struct resource gpmc_onenand_resource = { - .flags = IORESOURCE_MEM, -}; - -static struct platform_device gpmc_onenand_device = { - .name = "omap2-onenand", - .id = -1, - .num_resources = 1, - .resource = &gpmc_onenand_resource, -}; - -static void omap2_onenand_calc_async_timings(struct gpmc_timings *t, - struct gpmc_settings *s) -{ - struct gpmc_device_timings dev_t; - const int t_cer = 15; - const int t_avdp = 12; - const int t_aavdh = 7; - const int t_ce = 76; - const int t_aa = 76; - const int t_oe = 20; - const int t_cez = 20; /* max of t_cez, t_oez */ - const int t_wpl = 40; - const int t_wph = 30; - - memset(&dev_t, 0, sizeof(dev_t)); - - dev_t.t_avdp_r = max_t(int, t_avdp, t_cer) * 1000; - dev_t.t_avdp_w = dev_t.t_avdp_r; - dev_t.t_aavdh = t_aavdh * 1000; - dev_t.t_aa = t_aa * 1000; - dev_t.t_ce = t_ce * 1000; - dev_t.t_oe = t_oe * 1000; - dev_t.t_cez_r = t_cez * 1000; - dev_t.t_cez_w = dev_t.t_cez_r; - dev_t.t_wpl = t_wpl * 1000; - dev_t.t_wph = t_wph * 1000; - - gpmc_calc_timings(t, s, &dev_t); -} - -static void omap2_onenand_set_async_mode(void __iomem *onenand_base) -{ - u32 reg; - - /* Ensure sync read and sync write are disabled */ - reg = readw(onenand_base + ONENAND_REG_SYS_CFG1); - reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE; - writew(reg, onenand_base + ONENAND_REG_SYS_CFG1); -} - -static void set_onenand_cfg(void __iomem *onenand_base, - bool sr, bool sw, int latency) -{ - u32 reg = ONENAND_SYS_CFG1_RDY | ONENAND_SYS_CFG1_INT; - - reg |= (latency << ONENAND_SYS_CFG1_BRL_SHIFT) | - ONENAND_SYS_CFG1_BL_16; - if (latency > 5) - reg |= ONENAND_SYS_CFG1_HF; - if (latency > 7) - reg |= ONENAND_SYS_CFG1_VHF; - if (sr) - reg |= ONENAND_SYS_CFG1_SYNC_READ; - if (sw) - reg |= ONENAND_SYS_CFG1_SYNC_WRITE; - - writew(reg, onenand_base + ONENAND_REG_SYS_CFG1); -} - -static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg, - void __iomem *onenand_base) -{ - u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID); - int freq; - - switch ((ver >> 4) & 0xf) { - case 0: - freq = 40; - break; - case 1: - freq = 54; - break; - case 2: - freq = 66; - break; - case 3: - freq = 83; - break; - case 4: - freq = 104; - break; - default: - pr_err("onenand rate not detected, bad GPMC async timings?\n"); - freq = 0; - } - - return freq; -} - -static int omap2_onenand_calc_sync_timings(struct gpmc_timings *t, - struct gpmc_settings *s, - int freq) -{ - struct gpmc_device_timings dev_t; - const int t_cer = 15; - const int t_avdp = 12; - const int t_cez = 20; /* max of t_cez, t_oez */ - const int t_wpl = 40; - const int t_wph = 30; - int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo; - int div, gpmc_clk_ns, latency; - - if (!s->sync_read && !s->sync_write) - return 0; - - switch (freq) { - case 104: - min_gpmc_clk_period = 9600; /* 104 MHz */ - t_ces = 3; - t_avds = 4; - t_avdh = 2; - t_ach = 3; - t_aavdh = 6; - t_rdyo = 6; - break; - case 83: - min_gpmc_clk_period = 12000; /* 83 MHz */ - t_ces = 5; - t_avds = 4; - t_avdh = 2; - t_ach = 6; - t_aavdh = 6; - t_rdyo = 9; - break; - case 66: - min_gpmc_clk_period = 15000; /* 66 MHz */ - t_ces = 6; - t_avds = 5; - t_avdh = 2; - t_ach = 6; - t_aavdh = 6; - t_rdyo = 11; - break; - default: - min_gpmc_clk_period = 18500; /* 54 MHz */ - t_ces = 7; - t_avds = 7; - t_avdh = 7; - t_ach = 9; - t_aavdh = 7; - t_rdyo = 15; - s->sync_write = false; - s->burst_write = false; - break; - } - - div = gpmc_calc_divider(min_gpmc_clk_period); - gpmc_clk_ns = gpmc_ticks_to_ns(div); - if (gpmc_clk_ns < 12) /* >83 MHz */ - latency = 8; - else if (gpmc_clk_ns < 15) /* >66 MHz */ - latency = 6; - else if (gpmc_clk_ns >= 25) /* 40 MHz */ - latency = 3; - else - latency = 4; - - /* Set synchronous read timings */ - memset(&dev_t, 0, sizeof(dev_t)); - - if (!s->sync_write) { - dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000; - dev_t.t_wpl = t_wpl * 1000; - dev_t.t_wph = t_wph * 1000; - dev_t.t_aavdh = t_aavdh * 1000; - } - dev_t.ce_xdelay = true; - dev_t.avd_xdelay = true; - dev_t.oe_xdelay = true; - dev_t.we_xdelay = true; - dev_t.clk = min_gpmc_clk_period; - dev_t.t_bacc = dev_t.clk; - dev_t.t_ces = t_ces * 1000; - dev_t.t_avds = t_avds * 1000; - dev_t.t_avdh = t_avdh * 1000; - dev_t.t_ach = t_ach * 1000; - dev_t.cyc_iaa = (latency + 1); - dev_t.t_cez_r = t_cez * 1000; - dev_t.t_cez_w = dev_t.t_cez_r; - dev_t.cyc_aavdh_oe = 1; - dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period; - - gpmc_calc_timings(t, s, &dev_t); - - return latency; -} - -static int omap2_onenand_setup_async(void __iomem *onenand_base) -{ - struct gpmc_timings t; - struct gpmc_settings s; - int ret; - - /* - * Note that we need to keep sync_write set for the call to - * omap2_onenand_set_async_mode() to work to detect the onenand - * supported clock rate for the sync timings. - */ - gpmc_read_settings_dt(gpmc_onenand_data->of_node, &s); - s.sync_read = false; - s.sync_write = true; - - omap2_onenand_calc_async_timings(&t, &s); - - ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &s); - if (ret < 0) - return ret; - - ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t, &s); - if (ret < 0) - return ret; - - omap2_onenand_set_async_mode(onenand_base); - - return 0; -} - -static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr) -{ - int ret, latency, freq = *freq_ptr; - struct gpmc_timings t; - struct gpmc_settings s; - - if (!freq) { - /* Very first call freq is not known */ - freq = omap2_onenand_get_freq(gpmc_onenand_data, onenand_base); - if (!freq) - return -ENODEV; - } - - gpmc_read_settings_dt(gpmc_onenand_data->of_node, &s); - - latency = omap2_onenand_calc_sync_timings(&t, &s, freq); - if (latency > 0) { - ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &s); - if (ret < 0) - return ret; - - ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t, &s); - if (ret < 0) - return ret; - - set_onenand_cfg(onenand_base, s.sync_read, s.sync_write, - latency); - } - - *freq_ptr = freq; - - return 0; -} - -static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr) -{ - struct device *dev = &gpmc_onenand_device.dev; - int ret; - - ret = omap2_onenand_setup_async(onenand_base); - if (ret) { - dev_err(dev, "unable to set to async mode\n"); - return ret; - } - - ret = omap2_onenand_setup_sync(onenand_base, freq_ptr); - if (ret) - dev_err(dev, "unable to set to sync mode\n"); - return ret; -} - -int gpmc_omap_onenand_init(struct omap_onenand_platform_data *_onenand_data) -{ - gpmc_onenand_data = _onenand_data; - gpmc_onenand_data->onenand_setup = gpmc_onenand_setup; - gpmc_onenand_device.dev.platform_data = gpmc_onenand_data; - - if (cpu_is_omap34xx()) - gpmc_onenand_data->flags |= ONENAND_IN_OMAP34XX; - else - gpmc_onenand_data->flags &= ~ONENAND_IN_OMAP34XX; - - return 0; - -} - -int gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data) -{ - int err; - struct device *dev = &gpmc_onenand_device.dev; - - gpmc_omap_onenand_init(_onenand_data); - - err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE, - (unsigned long *)&gpmc_onenand_resource.start); - if (err < 0) { - dev_err(dev, "Cannot request GPMC CS %d, error %d\n", - gpmc_onenand_data->cs, err); - return err; - } - - gpmc_onenand_resource.end = gpmc_onenand_resource.start + - ONENAND_IO_SIZE - 1; - - err = platform_device_register(&gpmc_onenand_device); - if (err) { - dev_err(dev, "Unable to register OneNAND device\n"); - gpmc_cs_free(gpmc_onenand_data->cs); - } - - return err; -} diff --git a/include/linux/platform_data/mtd-onenand-omap2.h b/include/linux/platform_data/mtd-onenand-omap2.h deleted file mode 100644 index 56ff0e6f5ad1..000000000000 --- a/include/linux/platform_data/mtd-onenand-omap2.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (C) 2006 Nokia Corporation - * Author: Juha Yrjola - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __MTD_ONENAND_OMAP2_H -#define __MTD_ONENAND_OMAP2_H - -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> - -#define ONENAND_SYNC_READ (1 << 0) -#define ONENAND_SYNC_READWRITE (1 << 1) -#define ONENAND_IN_OMAP34XX (1 << 2) - -struct omap_onenand_platform_data { - int cs; - int gpio_irq; - struct mtd_partition *parts; - int nr_parts; - int (*onenand_setup)(void __iomem *, int *freq_ptr); - int dma_channel; - u8 flags; - u8 regulator_can_sleep; - u8 skip_initial_unlocking; - - /* for passing the partitions */ - struct device_node *of_node; -}; -#endif
Remove now dead code. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> --- arch/arm/mach-omap2/Makefile | 3 - arch/arm/mach-omap2/gpmc-onenand.c | 349 ------------------------ include/linux/platform_data/mtd-onenand-omap2.h | 34 --- 3 files changed, 386 deletions(-)