| Message ID | 20170929131357.26796-1-Eugeniy.Paltsev@synopsys.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
Hi folks, On 09/29/2017 06:13 AM, Eugeniy Paltsev wrote: > Add option to set initial output frequency of plls via > "clock-frequency" property in pll's device tree node. > This frequency will be set while pll driver probed. > > The usage example is setting CPU clock frequency on boot > See discussion: > https://www.mail-archive.com/linux-snps-arc@lists.infradead.org/msg02689.html Any yay / nay on this please ? I guess some de-duplication is in order anyways but is the overall approach sane ? Additional background / context in thread http://lists.infradead.org/pipermail/linux-snps-arc/2017-September/002900.html Thx, -Vineet > > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> > --- > .../bindings/clock/snps,hsdk-pll-clock.txt | 5 ++++ > .../devicetree/bindings/clock/snps,pll-clock.txt | 5 ++++ > drivers/clk/axs10x/pll_clock.c | 34 ++++++++++++++++++++-- > drivers/clk/clk-hsdk-pll.c | 34 ++++++++++++++++++++-- > 4 files changed, 74 insertions(+), 4 deletions(-) > > diff --git a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt > index c56c755..5703059 100644 > --- a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt > +++ b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt > @@ -13,6 +13,10 @@ Required properties: > - clocks: shall be the input parent clock phandle for the PLL. > - #clock-cells: from common clock binding; Should always be set to 0. > > +Optional properties: > +- clock-frequency: output frequency generated by pll in Hz which will be set > +while probing. Should be a single cell. > + > Example: > input_clk: input-clk { > clock-frequency = <33333333>; > @@ -25,4 +29,5 @@ Example: > reg = <0x00 0x10>; > #clock-cells = <0>; > clocks = <&input_clk>; > + clock-frequency = <1000000000>; > }; > diff --git a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt > index 11fe487..5908f99 100644 > --- a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt > +++ b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt > @@ -13,6 +13,10 @@ registers and second for corresponding LOCK CGU register. > - clocks: shall be the input parent clock phandle for the PLL. > - #clock-cells: from common clock binding; Should always be set to 0. > > +Optional properties: > +- clock-frequency: output frequency generated by pll in Hz which will be set > +while probing. Should be a single cell. > + > Example: > input-clk: input-clk { > clock-frequency = <33333333>; > @@ -25,4 +29,5 @@ Example: > reg = <0x80 0x10>, <0x100 0x10>; > #clock-cells = <0>; > clocks = <&input-clk>; > + clock-frequency = <100000000>; > }; > diff --git a/drivers/clk/axs10x/pll_clock.c b/drivers/clk/axs10x/pll_clock.c > index 25d8c24..3f4345d 100644 > --- a/drivers/clk/axs10x/pll_clock.c > +++ b/drivers/clk/axs10x/pll_clock.c > @@ -11,6 +11,7 @@ > #include <linux/platform_device.h> > #include <linux/module.h> > #include <linux/clk-provider.h> > +#include <linux/clk.h> > #include <linux/delay.h> > #include <linux/err.h> > #include <linux/device.h> > @@ -215,6 +216,25 @@ static const struct clk_ops axs10x_pll_ops = { > .set_rate = axs10x_pll_set_rate, > }; > > +static void set_pll_rate_from_of(struct clk *clk, struct device_node *node) > +{ > + u32 requested_rate; > + > + /* If we specify initial pll output frequency try to set it */ > + if (of_property_read_u32(node, "clock-frequency", &requested_rate)) > + return; > + > + if (clk_prepare_enable(clk)) { > + pr_err("Cannot enable %s clock.\n", node->name); > + return; > + } > + > + if (clk_set_rate(clk, requested_rate)) > + pr_err("Cannot set %s clock rate.\n", node->name); > + > + pr_debug("Set %s clock to %u\n", node->name, requested_rate); > +} > + > static int axs10x_pll_clk_probe(struct platform_device *pdev) > { > struct device *dev = &pdev->dev; > @@ -258,8 +278,15 @@ static int axs10x_pll_clk_probe(struct platform_device *pdev) > return ret; > } > > - return of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, > - &pll_clk->hw); > + ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, > + &pll_clk->hw); > + if (ret) > + return ret; > + > + /* If we specify initial pll output frequency in dts try to set it */ > + set_pll_rate_from_of(pll_clk->hw.clk, dev->of_node); > + > + return 0; > } > > static int axs10x_pll_clk_remove(struct platform_device *pdev) > @@ -311,6 +338,9 @@ static void __init of_axs10x_pll_clk_setup(struct device_node *node) > goto err_unregister_clk; > } > > + /* If we specify initial pll output frequency in dts try to set it */ > + set_pll_rate_from_of(pll_clk->hw.clk, node); > + > return; > > err_unregister_clk: > diff --git a/drivers/clk/clk-hsdk-pll.c b/drivers/clk/clk-hsdk-pll.c > index bbf23717..74fd006 100644 > --- a/drivers/clk/clk-hsdk-pll.c > +++ b/drivers/clk/clk-hsdk-pll.c > @@ -9,6 +9,7 @@ > */ > > #include <linux/clk-provider.h> > +#include <linux/clk.h> > #include <linux/delay.h> > #include <linux/device.h> > #include <linux/err.h> > @@ -295,6 +296,25 @@ static const struct clk_ops hsdk_pll_ops = { > .set_rate = hsdk_pll_set_rate, > }; > > +static void set_pll_rate_from_of(struct clk *clk, struct device_node *node) > +{ > + u32 requested_rate; > + > + /* If we specify initial pll output frequency try to set it */ > + if (of_property_read_u32(node, "clock-frequency", &requested_rate)) > + return; > + > + if (clk_prepare_enable(clk)) { > + pr_err("Cannot enable %s clock.\n", node->name); > + return; > + } > + > + if (clk_set_rate(clk, requested_rate)) > + pr_err("Cannot set %s clock rate.\n", node->name); > + > + pr_debug("Set %s clock to %u\n", node->name, requested_rate); > +} > + > static int hsdk_pll_clk_probe(struct platform_device *pdev) > { > int ret; > @@ -340,8 +360,15 @@ static int hsdk_pll_clk_probe(struct platform_device *pdev) > return ret; > } > > - return of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, > - &pll_clk->hw); > + ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, > + &pll_clk->hw); > + if (ret) > + return ret; > + > + /* If we specify initial pll output frequency in dts try to set it */ > + set_pll_rate_from_of(pll_clk->hw.clk, dev->of_node); > + > + return 0; > } > > static int hsdk_pll_clk_remove(struct platform_device *pdev) > @@ -400,6 +427,9 @@ static void __init of_hsdk_pll_clk_setup(struct device_node *node) > goto err_unmap_spec_regs; > } > > + /* If we specify initial pll output frequency in dts try to set it */ > + set_pll_rate_from_of(pll_clk->hw.clk, node); > + > return; > > err_unmap_spec_regs: > -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
SGkgU3RlcGhlbiwgTWljaGFlbCwNCg0KUGxlYXNlIHRyZWF0IHRoaXMgbWVzc2FnZSBhcyBhIHBv bGl0ZSByZW1pbmRlciB0byByZXZpZXcgbXkgcGF0Y2guDQpJdCB3b3VsZCBiZSByZWFsbHkgbmlj ZSB0byBzZWUgdGhpcyBwYXRjaCBpbiA0LjE1Lg0KDQpUaGFua3MuDQoNCk9uIEZyaSwgMjAxNy0w OS0yOSBhdCAxNjoxMyArMDMwMCwgRXVnZW5peSBQYWx0c2V2IHdyb3RlOg0KPiBBZGQgb3B0aW9u IHRvIHNldCBpbml0aWFsIG91dHB1dCBmcmVxdWVuY3kgb2YgcGxscyB2aWENCj4gImNsb2NrLWZy ZXF1ZW5jeSIgcHJvcGVydHkgaW4gcGxsJ3MgZGV2aWNlIHRyZWUgbm9kZS4NCj4gVGhpcyBmcmVx dWVuY3kgd2lsbCBiZSBzZXQgd2hpbGUgcGxsIGRyaXZlciBwcm9iZWQuDQo+IA0KPiBUaGUgdXNh Z2UgZXhhbXBsZSBpcyBzZXR0aW5nIENQVSBjbG9jayBmcmVxdWVuY3kgb24gYm9vdA0KPiBTZWUg ZGlzY3Vzc2lvbjoNCj4gaHR0cHM6Ly93d3cubWFpbC1hcmNoaXZlLmNvbS9saW51eC1zbnBzLWFy Y0BsaXN0cy5pbmZyYWRlYWQub3JnL21zZzAyNjg5Lmh0bWwNCj4gDQo+IFNpZ25lZC1vZmYtYnk6 IEV1Z2VuaXkgUGFsdHNldiA8RXVnZW5peS5QYWx0c2V2QHN5bm9wc3lzLmNvbT4NCj4gLS0tDQo+ IMKgLi4uL2JpbmRpbmdzL2Nsb2NrL3NucHMsaHNkay1wbGwtY2xvY2sudHh0wqDCoMKgwqDCoMKg wqDCoMKgfMKgwqA1ICsrKysNCj4gwqAuLi4vZGV2aWNldHJlZS9iaW5kaW5ncy9jbG9jay9zbnBz LHBsbC1jbG9jay50eHTCoMKgwqB8wqDCoDUgKysrKw0KPiDCoGRyaXZlcnMvY2xrL2F4czEweC9w bGxfY2xvY2suY8KgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoHwgMzQg KysrKysrKysrKysrKysrKysrKystLQ0KPiDCoGRyaXZlcnMvY2xrL2Nsay1oc2RrLXBsbC5jwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqB8IDM0ICsrKysr KysrKysrKysrKysrKysrLS0NCj4gwqA0IGZpbGVzIGNoYW5nZWQsIDc0IGluc2VydGlvbnMoKyks IDQgZGVsZXRpb25zKC0pDQo+IA0KPiBkaWZmIC0tZ2l0IGEvRG9jdW1lbnRhdGlvbi9kZXZpY2V0 cmVlL2JpbmRpbmdzL2Nsb2NrL3NucHMsaHNkay1wbGwtY2xvY2sudHh0IGIvRG9jdW1lbnRhdGlv bi9kZXZpY2V0cmVlL2JpbmRpbmdzL2Nsb2NrL3NucHMsaHNkay1wbGwtY2xvY2sudHh0DQo+IGlu ZGV4IGM1NmM3NTUuLjU3MDMwNTkgMTAwNjQ0DQo+IC0tLSBhL0RvY3VtZW50YXRpb24vZGV2aWNl dHJlZS9iaW5kaW5ncy9jbG9jay9zbnBzLGhzZGstcGxsLWNsb2NrLnR4dA0KPiArKysgYi9Eb2N1 bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvY2xvY2svc25wcyxoc2RrLXBsbC1jbG9jay50 eHQNCj4gQEAgLTEzLDYgKzEzLDEwIEBAIFJlcXVpcmVkIHByb3BlcnRpZXM6DQo+IMKgLSBjbG9j a3M6IHNoYWxsIGJlIHRoZSBpbnB1dCBwYXJlbnQgY2xvY2sgcGhhbmRsZSBmb3IgdGhlIFBMTC4N Cj4gwqAtICNjbG9jay1jZWxsczogZnJvbSBjb21tb24gY2xvY2sgYmluZGluZzsgU2hvdWxkIGFs d2F5cyBiZSBzZXQgdG8gMC4NCj4gwqANCj4gK09wdGlvbmFsIHByb3BlcnRpZXM6DQo+ICstIGNs b2NrLWZyZXF1ZW5jeTogb3V0cHV0IGZyZXF1ZW5jeSBnZW5lcmF0ZWQgYnkgcGxsIGluIEh6IHdo aWNoIHdpbGwgYmUgc2V0DQo+ICt3aGlsZSBwcm9iaW5nLiBTaG91bGQgYmUgYSBzaW5nbGUgY2Vs bC4NCj4gKw0KPiDCoEV4YW1wbGU6DQo+IMKgCWlucHV0X2NsazogaW5wdXQtY2xrIHsNCj4gwqAJ CWNsb2NrLWZyZXF1ZW5jeSA9IDwzMzMzMzMzMz47DQo+IEBAIC0yNSw0ICsyOSw1IEBAIEV4YW1w bGU6DQo+IMKgCQlyZWcgPSA8MHgwMCAweDEwPjsNCj4gwqAJCSNjbG9jay1jZWxscyA9IDwwPjsN Cj4gwqAJCWNsb2NrcyA9IDwmaW5wdXRfY2xrPjsNCj4gKwkJY2xvY2stZnJlcXVlbmN5ID0gPDEw MDAwMDAwMDA+Ow0KPiDCoAl9Ow0KPiBkaWZmIC0tZ2l0IGEvRG9jdW1lbnRhdGlvbi9kZXZpY2V0 cmVlL2JpbmRpbmdzL2Nsb2NrL3NucHMscGxsLWNsb2NrLnR4dCBiL0RvY3VtZW50YXRpb24vZGV2 aWNldHJlZS9iaW5kaW5ncy9jbG9jay9zbnBzLHBsbC1jbG9jay50eHQNCj4gaW5kZXggMTFmZTQ4 Ny4uNTkwOGY5OSAxMDA2NDQNCj4gLS0tIGEvRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRp bmdzL2Nsb2NrL3NucHMscGxsLWNsb2NrLnR4dA0KPiArKysgYi9Eb2N1bWVudGF0aW9uL2Rldmlj ZXRyZWUvYmluZGluZ3MvY2xvY2svc25wcyxwbGwtY2xvY2sudHh0DQo+IEBAIC0xMyw2ICsxMywx MCBAQCByZWdpc3RlcnMgYW5kIHNlY29uZCBmb3IgY29ycmVzcG9uZGluZyBMT0NLIENHVSByZWdp c3Rlci4NCj4gwqAtIGNsb2Nrczogc2hhbGwgYmUgdGhlIGlucHV0IHBhcmVudCBjbG9jayBwaGFu ZGxlIGZvciB0aGUgUExMLg0KPiDCoC0gI2Nsb2NrLWNlbGxzOiBmcm9tIGNvbW1vbiBjbG9jayBi aW5kaW5nOyBTaG91bGQgYWx3YXlzIGJlIHNldCB0byAwLg0KPiDCoA0KPiArT3B0aW9uYWwgcHJv cGVydGllczoNCj4gKy0gY2xvY2stZnJlcXVlbmN5OiBvdXRwdXQgZnJlcXVlbmN5IGdlbmVyYXRl ZCBieSBwbGwgaW4gSHogd2hpY2ggd2lsbCBiZSBzZXQNCj4gK3doaWxlIHByb2JpbmcuIFNob3Vs ZCBiZSBhIHNpbmdsZSBjZWxsLg0KPiArDQo+IMKgRXhhbXBsZToNCj4gwqAJaW5wdXQtY2xrOiBp bnB1dC1jbGsgew0KPiDCoAkJY2xvY2stZnJlcXVlbmN5ID0gPDMzMzMzMzMzPjsNCj4gQEAgLTI1 LDQgKzI5LDUgQEAgRXhhbXBsZToNCj4gwqAJCXJlZyA9IDwweDgwIDB4MTA+LCA8MHgxMDAgMHgx MD47DQo+IMKgCQkjY2xvY2stY2VsbHMgPSA8MD47DQo+IMKgCQljbG9ja3MgPSA8JmlucHV0LWNs az47DQo+ICsJCWNsb2NrLWZyZXF1ZW5jeSA9IDwxMDAwMDAwMDA+Ow0KPiDCoAl9Ow0KPiBkaWZm IC0tZ2l0IGEvZHJpdmVycy9jbGsvYXhzMTB4L3BsbF9jbG9jay5jIGIvZHJpdmVycy9jbGsvYXhz MTB4L3BsbF9jbG9jay5jDQo+IGluZGV4IDI1ZDhjMjQuLjNmNDM0NWQgMTAwNjQ0DQo+IC0tLSBh L2RyaXZlcnMvY2xrL2F4czEweC9wbGxfY2xvY2suYw0KPiArKysgYi9kcml2ZXJzL2Nsay9heHMx MHgvcGxsX2Nsb2NrLmMNCj4gQEAgLTExLDYgKzExLDcgQEANCj4gwqAjaW5jbHVkZSA8bGludXgv cGxhdGZvcm1fZGV2aWNlLmg+DQo+IMKgI2luY2x1ZGUgPGxpbnV4L21vZHVsZS5oPg0KPiDCoCNp bmNsdWRlIDxsaW51eC9jbGstcHJvdmlkZXIuaD4NCj4gKyNpbmNsdWRlIDxsaW51eC9jbGsuaD4N Cj4gwqAjaW5jbHVkZSA8bGludXgvZGVsYXkuaD4NCj4gwqAjaW5jbHVkZSA8bGludXgvZXJyLmg+ DQo+IMKgI2luY2x1ZGUgPGxpbnV4L2RldmljZS5oPg0KPiBAQCAtMjE1LDYgKzIxNiwyNSBAQCBz dGF0aWMgY29uc3Qgc3RydWN0IGNsa19vcHMgYXhzMTB4X3BsbF9vcHMgPSB7DQo+IMKgCS5zZXRf cmF0ZSA9IGF4czEweF9wbGxfc2V0X3JhdGUsDQo+IMKgfTsNCj4gwqANCj4gK3N0YXRpYyB2b2lk IHNldF9wbGxfcmF0ZV9mcm9tX29mKHN0cnVjdCBjbGsgKmNsaywgc3RydWN0IGRldmljZV9ub2Rl ICpub2RlKQ0KPiArew0KPiArCXUzMiByZXF1ZXN0ZWRfcmF0ZTsNCj4gKw0KPiArCS8qIElmIHdl IHNwZWNpZnkgaW5pdGlhbCBwbGwgb3V0cHV0IGZyZXF1ZW5jeSB0cnkgdG8gc2V0IGl0ICovDQo+ ICsJaWYgKG9mX3Byb3BlcnR5X3JlYWRfdTMyKG5vZGUsICJjbG9jay1mcmVxdWVuY3kiLCAmcmVx dWVzdGVkX3JhdGUpKQ0KPiArCQlyZXR1cm47DQo+ICsNCj4gKwlpZiAoY2xrX3ByZXBhcmVfZW5h YmxlKGNsaykpIHsNCj4gKwkJcHJfZXJyKCJDYW5ub3QgZW5hYmxlICVzIGNsb2NrLlxuIiwgbm9k ZS0+bmFtZSk7DQo+ICsJCXJldHVybjsNCj4gKwl9DQo+ICsNCj4gKwlpZiAoY2xrX3NldF9yYXRl KGNsaywgcmVxdWVzdGVkX3JhdGUpKQ0KPiArCQlwcl9lcnIoIkNhbm5vdCBzZXQgJXMgY2xvY2sg cmF0ZS5cbiIsIG5vZGUtPm5hbWUpOw0KPiArDQo+ICsJcHJfZGVidWcoIlNldCAlcyBjbG9jayB0 byAldVxuIiwgbm9kZS0+bmFtZSwgcmVxdWVzdGVkX3JhdGUpOw0KPiArfQ0KPiArDQo+IMKgc3Rh dGljIGludCBheHMxMHhfcGxsX2Nsa19wcm9iZShzdHJ1Y3QgcGxhdGZvcm1fZGV2aWNlICpwZGV2 KQ0KPiDCoHsNCj4gwqAJc3RydWN0IGRldmljZSAqZGV2ID0gJnBkZXYtPmRldjsNCj4gQEAgLTI1 OCw4ICsyNzgsMTUgQEAgc3RhdGljIGludCBheHMxMHhfcGxsX2Nsa19wcm9iZShzdHJ1Y3QgcGxh dGZvcm1fZGV2aWNlICpwZGV2KQ0KPiDCoAkJcmV0dXJuIHJldDsNCj4gwqAJfQ0KPiDCoA0KPiAt CXJldHVybiBvZl9jbGtfYWRkX2h3X3Byb3ZpZGVyKGRldi0+b2Zfbm9kZSwgb2ZfY2xrX2h3X3Np bXBsZV9nZXQsDQo+IC0JCQkmcGxsX2Nsay0+aHcpOw0KPiArCXJldCA9wqDCoG9mX2Nsa19hZGRf aHdfcHJvdmlkZXIoZGV2LT5vZl9ub2RlLCBvZl9jbGtfaHdfc2ltcGxlX2dldCwNCj4gKwkJCQnC oMKgwqDCoMKgwqAmcGxsX2Nsay0+aHcpOw0KPiArCWlmIChyZXQpDQo+ICsJCXJldHVybiByZXQ7 DQo+ICsNCj4gKwkvKiBJZiB3ZSBzcGVjaWZ5IGluaXRpYWwgcGxsIG91dHB1dCBmcmVxdWVuY3kg aW4gZHRzIHRyeSB0byBzZXQgaXQgKi8NCj4gKwlzZXRfcGxsX3JhdGVfZnJvbV9vZihwbGxfY2xr LT5ody5jbGssIGRldi0+b2Zfbm9kZSk7DQo+ICsNCj4gKwlyZXR1cm4gMDsNCj4gwqB9DQo+IMKg DQo+IMKgc3RhdGljIGludCBheHMxMHhfcGxsX2Nsa19yZW1vdmUoc3RydWN0IHBsYXRmb3JtX2Rl dmljZSAqcGRldikNCj4gQEAgLTMxMSw2ICszMzgsOSBAQCBzdGF0aWMgdm9pZCBfX2luaXQgb2Zf YXhzMTB4X3BsbF9jbGtfc2V0dXAoc3RydWN0IGRldmljZV9ub2RlICpub2RlKQ0KPiDCoAkJZ290 byBlcnJfdW5yZWdpc3Rlcl9jbGs7DQo+IMKgCX0NCj4gwqANCj4gKwkvKiBJZiB3ZSBzcGVjaWZ5 IGluaXRpYWwgcGxsIG91dHB1dCBmcmVxdWVuY3kgaW4gZHRzIHRyeSB0byBzZXQgaXQgKi8NCj4g KwlzZXRfcGxsX3JhdGVfZnJvbV9vZihwbGxfY2xrLT5ody5jbGssIG5vZGUpOw0KPiArDQo+IMKg CXJldHVybjsNCj4gwqANCj4gwqBlcnJfdW5yZWdpc3Rlcl9jbGs6DQo+IGRpZmYgLS1naXQgYS9k cml2ZXJzL2Nsay9jbGstaHNkay1wbGwuYyBiL2RyaXZlcnMvY2xrL2Nsay1oc2RrLXBsbC5jDQo+ IGluZGV4IGJiZjIzNzE3Li43NGZkMDA2IDEwMDY0NA0KPiAtLS0gYS9kcml2ZXJzL2Nsay9jbGst aHNkay1wbGwuYw0KPiArKysgYi9kcml2ZXJzL2Nsay9jbGstaHNkay1wbGwuYw0KPiBAQCAtOSw2 ICs5LDcgQEANCj4gwqAgKi8NCj4gwqANCj4gwqAjaW5jbHVkZSA8bGludXgvY2xrLXByb3ZpZGVy Lmg+DQo+ICsjaW5jbHVkZSA8bGludXgvY2xrLmg+DQo+IMKgI2luY2x1ZGUgPGxpbnV4L2RlbGF5 Lmg+DQo+IMKgI2luY2x1ZGUgPGxpbnV4L2RldmljZS5oPg0KPiDCoCNpbmNsdWRlIDxsaW51eC9l cnIuaD4NCj4gQEAgLTI5NSw2ICsyOTYsMjUgQEAgc3RhdGljIGNvbnN0IHN0cnVjdCBjbGtfb3Bz IGhzZGtfcGxsX29wcyA9IHsNCj4gwqAJLnNldF9yYXRlID0gaHNka19wbGxfc2V0X3JhdGUsDQo+ IMKgfTsNCj4gwqANCj4gK3N0YXRpYyB2b2lkIHNldF9wbGxfcmF0ZV9mcm9tX29mKHN0cnVjdCBj bGsgKmNsaywgc3RydWN0IGRldmljZV9ub2RlICpub2RlKQ0KPiArew0KPiArCXUzMiByZXF1ZXN0 ZWRfcmF0ZTsNCj4gKw0KPiArCS8qIElmIHdlIHNwZWNpZnkgaW5pdGlhbCBwbGwgb3V0cHV0IGZy ZXF1ZW5jeSB0cnkgdG8gc2V0IGl0ICovDQo+ICsJaWYgKG9mX3Byb3BlcnR5X3JlYWRfdTMyKG5v ZGUsICJjbG9jay1mcmVxdWVuY3kiLCAmcmVxdWVzdGVkX3JhdGUpKQ0KPiArCQlyZXR1cm47DQo+ ICsNCj4gKwlpZiAoY2xrX3ByZXBhcmVfZW5hYmxlKGNsaykpIHsNCj4gKwkJcHJfZXJyKCJDYW5u b3QgZW5hYmxlICVzIGNsb2NrLlxuIiwgbm9kZS0+bmFtZSk7DQo+ICsJCXJldHVybjsNCj4gKwl9 DQo+ICsNCj4gKwlpZiAoY2xrX3NldF9yYXRlKGNsaywgcmVxdWVzdGVkX3JhdGUpKQ0KPiArCQlw cl9lcnIoIkNhbm5vdCBzZXQgJXMgY2xvY2sgcmF0ZS5cbiIsIG5vZGUtPm5hbWUpOw0KPiArDQo+ ICsJcHJfZGVidWcoIlNldCAlcyBjbG9jayB0byAldVxuIiwgbm9kZS0+bmFtZSwgcmVxdWVzdGVk X3JhdGUpOw0KPiArfQ0KPiArDQo+IMKgc3RhdGljIGludCBoc2RrX3BsbF9jbGtfcHJvYmUoc3Ry dWN0IHBsYXRmb3JtX2RldmljZSAqcGRldikNCj4gwqB7DQo+IMKgCWludCByZXQ7DQo+IEBAIC0z NDAsOCArMzYwLDE1IEBAIHN0YXRpYyBpbnQgaHNka19wbGxfY2xrX3Byb2JlKHN0cnVjdCBwbGF0 Zm9ybV9kZXZpY2UgKnBkZXYpDQo+IMKgCQlyZXR1cm4gcmV0Ow0KPiDCoAl9DQo+IMKgDQo+IC0J cmV0dXJuIG9mX2Nsa19hZGRfaHdfcHJvdmlkZXIoZGV2LT5vZl9ub2RlLCBvZl9jbGtfaHdfc2lt cGxlX2dldCwNCj4gLQkJCSZwbGxfY2xrLT5odyk7DQo+ICsJcmV0ID3CoMKgb2ZfY2xrX2FkZF9o d19wcm92aWRlcihkZXYtPm9mX25vZGUsIG9mX2Nsa19od19zaW1wbGVfZ2V0LA0KPiArCQkJCcKg wqDCoMKgwqDCoCZwbGxfY2xrLT5odyk7DQo+ICsJaWYgKHJldCkNCj4gKwkJcmV0dXJuIHJldDsN Cj4gKw0KPiArCS8qIElmIHdlIHNwZWNpZnkgaW5pdGlhbCBwbGwgb3V0cHV0IGZyZXF1ZW5jeSBp biBkdHMgdHJ5IHRvIHNldCBpdCAqLw0KPiArCXNldF9wbGxfcmF0ZV9mcm9tX29mKHBsbF9jbGst Pmh3LmNsaywgZGV2LT5vZl9ub2RlKTsNCj4gKw0KPiArCXJldHVybiAwOw0KPiDCoH0NCj4gwqAN Cj4gwqBzdGF0aWMgaW50IGhzZGtfcGxsX2Nsa19yZW1vdmUoc3RydWN0IHBsYXRmb3JtX2Rldmlj ZSAqcGRldikNCj4gQEAgLTQwMCw2ICs0MjcsOSBAQCBzdGF0aWMgdm9pZCBfX2luaXQgb2ZfaHNk a19wbGxfY2xrX3NldHVwKHN0cnVjdCBkZXZpY2Vfbm9kZSAqbm9kZSkNCj4gwqAJCWdvdG8gZXJy X3VubWFwX3NwZWNfcmVnczsNCj4gwqAJfQ0KPiDCoA0KPiArCS8qIElmIHdlIHNwZWNpZnkgaW5p dGlhbCBwbGwgb3V0cHV0IGZyZXF1ZW5jeSBpbiBkdHMgdHJ5IHRvIHNldCBpdCAqLw0KPiArCXNl dF9wbGxfcmF0ZV9mcm9tX29mKHBsbF9jbGstPmh3LmNsaywgbm9kZSk7DQo+ICsNCj4gwqAJcmV0 dXJuOw0KPiDCoA0KPiDCoGVycl91bm1hcF9zcGVjX3JlZ3M6DQotLSANCsKgRXVnZW5peSBQYWx0 c2V2 -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 11/13, Eugeniy Paltsev wrote: > Hi Stephen, Michael, > > Please treat this message as a polite reminder to review my patch. > It would be really nice to see this patch in 4.15. Sorry I don't have this in my queue. It might make v4.15 but the mere window is open now and I lost this patch somehow so hopefully I can throw it into the pile.
diff --git a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt index c56c755..5703059 100644 --- a/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt +++ b/Documentation/devicetree/bindings/clock/snps,hsdk-pll-clock.txt @@ -13,6 +13,10 @@ Required properties: - clocks: shall be the input parent clock phandle for the PLL. - #clock-cells: from common clock binding; Should always be set to 0. +Optional properties: +- clock-frequency: output frequency generated by pll in Hz which will be set +while probing. Should be a single cell. + Example: input_clk: input-clk { clock-frequency = <33333333>; @@ -25,4 +29,5 @@ Example: reg = <0x00 0x10>; #clock-cells = <0>; clocks = <&input_clk>; + clock-frequency = <1000000000>; }; diff --git a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt index 11fe487..5908f99 100644 --- a/Documentation/devicetree/bindings/clock/snps,pll-clock.txt +++ b/Documentation/devicetree/bindings/clock/snps,pll-clock.txt @@ -13,6 +13,10 @@ registers and second for corresponding LOCK CGU register. - clocks: shall be the input parent clock phandle for the PLL. - #clock-cells: from common clock binding; Should always be set to 0. +Optional properties: +- clock-frequency: output frequency generated by pll in Hz which will be set +while probing. Should be a single cell. + Example: input-clk: input-clk { clock-frequency = <33333333>; @@ -25,4 +29,5 @@ Example: reg = <0x80 0x10>, <0x100 0x10>; #clock-cells = <0>; clocks = <&input-clk>; + clock-frequency = <100000000>; }; diff --git a/drivers/clk/axs10x/pll_clock.c b/drivers/clk/axs10x/pll_clock.c index 25d8c24..3f4345d 100644 --- a/drivers/clk/axs10x/pll_clock.c +++ b/drivers/clk/axs10x/pll_clock.c @@ -11,6 +11,7 @@ #include <linux/platform_device.h> #include <linux/module.h> #include <linux/clk-provider.h> +#include <linux/clk.h> #include <linux/delay.h> #include <linux/err.h> #include <linux/device.h> @@ -215,6 +216,25 @@ static const struct clk_ops axs10x_pll_ops = { .set_rate = axs10x_pll_set_rate, }; +static void set_pll_rate_from_of(struct clk *clk, struct device_node *node) +{ + u32 requested_rate; + + /* If we specify initial pll output frequency try to set it */ + if (of_property_read_u32(node, "clock-frequency", &requested_rate)) + return; + + if (clk_prepare_enable(clk)) { + pr_err("Cannot enable %s clock.\n", node->name); + return; + } + + if (clk_set_rate(clk, requested_rate)) + pr_err("Cannot set %s clock rate.\n", node->name); + + pr_debug("Set %s clock to %u\n", node->name, requested_rate); +} + static int axs10x_pll_clk_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -258,8 +278,15 @@ static int axs10x_pll_clk_probe(struct platform_device *pdev) return ret; } - return of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, - &pll_clk->hw); + ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, + &pll_clk->hw); + if (ret) + return ret; + + /* If we specify initial pll output frequency in dts try to set it */ + set_pll_rate_from_of(pll_clk->hw.clk, dev->of_node); + + return 0; } static int axs10x_pll_clk_remove(struct platform_device *pdev) @@ -311,6 +338,9 @@ static void __init of_axs10x_pll_clk_setup(struct device_node *node) goto err_unregister_clk; } + /* If we specify initial pll output frequency in dts try to set it */ + set_pll_rate_from_of(pll_clk->hw.clk, node); + return; err_unregister_clk: diff --git a/drivers/clk/clk-hsdk-pll.c b/drivers/clk/clk-hsdk-pll.c index bbf23717..74fd006 100644 --- a/drivers/clk/clk-hsdk-pll.c +++ b/drivers/clk/clk-hsdk-pll.c @@ -9,6 +9,7 @@ */ #include <linux/clk-provider.h> +#include <linux/clk.h> #include <linux/delay.h> #include <linux/device.h> #include <linux/err.h> @@ -295,6 +296,25 @@ static const struct clk_ops hsdk_pll_ops = { .set_rate = hsdk_pll_set_rate, }; +static void set_pll_rate_from_of(struct clk *clk, struct device_node *node) +{ + u32 requested_rate; + + /* If we specify initial pll output frequency try to set it */ + if (of_property_read_u32(node, "clock-frequency", &requested_rate)) + return; + + if (clk_prepare_enable(clk)) { + pr_err("Cannot enable %s clock.\n", node->name); + return; + } + + if (clk_set_rate(clk, requested_rate)) + pr_err("Cannot set %s clock rate.\n", node->name); + + pr_debug("Set %s clock to %u\n", node->name, requested_rate); +} + static int hsdk_pll_clk_probe(struct platform_device *pdev) { int ret; @@ -340,8 +360,15 @@ static int hsdk_pll_clk_probe(struct platform_device *pdev) return ret; } - return of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, - &pll_clk->hw); + ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, + &pll_clk->hw); + if (ret) + return ret; + + /* If we specify initial pll output frequency in dts try to set it */ + set_pll_rate_from_of(pll_clk->hw.clk, dev->of_node); + + return 0; } static int hsdk_pll_clk_remove(struct platform_device *pdev) @@ -400,6 +427,9 @@ static void __init of_hsdk_pll_clk_setup(struct device_node *node) goto err_unmap_spec_regs; } + /* If we specify initial pll output frequency in dts try to set it */ + set_pll_rate_from_of(pll_clk->hw.clk, node); + return; err_unmap_spec_regs:
Add option to set initial output frequency of plls via "clock-frequency" property in pll's device tree node. This frequency will be set while pll driver probed. The usage example is setting CPU clock frequency on boot See discussion: https://www.mail-archive.com/linux-snps-arc@lists.infradead.org/msg02689.html Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> --- .../bindings/clock/snps,hsdk-pll-clock.txt | 5 ++++ .../devicetree/bindings/clock/snps,pll-clock.txt | 5 ++++ drivers/clk/axs10x/pll_clock.c | 34 ++++++++++++++++++++-- drivers/clk/clk-hsdk-pll.c | 34 ++++++++++++++++++++-- 4 files changed, 74 insertions(+), 4 deletions(-)