| Message ID | 1510662479-9550-1-git-send-email-xuyiping@hisilicon.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi, On 14/11/17 12:49, Alexander Shishkin wrote: > On Tue, Nov 14, 2017 at 08:27:59PM +0800, Xu YiPing wrote: >> bus access read/write events are not supported in A73, and the definition >> is duplicated, so delete it. > > In the changelog, it would be nice to mention the commit that added these: > > 5561b6c5e9813 ("arm64: perf: add support for Cortex-A73") > > Also it's not clear what is this new statement based on. The original > commit at least references a TRM document. > I re-checked the TRM for this core and Xu is right, the BUS_ACCESS events are not available on Cortex-A73. Plus those entries are duplicated, I think something went wrong when I rebased the patch. So I think this new patch is doing the right thing. Thanks for catching that. Cheers,
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index 9eaef51..3affca3 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -262,12 +262,6 @@ static const unsigned armv8_a73_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD, [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR, - - [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD, - [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR, - - [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD, - [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR, }; static const unsigned armv8_thunder_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
bus access read/write events are not supported in A73, and the definition is duplicated, so delete it. Signed-off-by: Xu YiPing <xuyiping@hisilicon.com> --- arch/arm64/kernel/perf_event.c | 6 ------ 1 file changed, 6 deletions(-)