| Message ID | 20171201021700.13504-1-james.ausmus@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Dec 01, 2017 at 02:17:00AM +0000, James Ausmus wrote: > Without masking out the old value, we can end up pointing the DDI to a > disabled PLL, which makes the system fall over. Mask out the previous > value before setting the PLL to DDI mapping. > > This can be observed by running igt/testdisplay with both an eDP and > HDMI/DP output active. > > v2: Add the Bugzilla link > > Fixes: 555e38d273172 ("drm/i915/cnl: DDI - PLL mapping") > Testcase: igt/testdisplay > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103997 > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Cc: Matt Atwood <matthew.s.atwood@intel.com> > Signed-off-by: James Ausmus <james.ausmus@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Tested-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Bug-introduced-by: Rodrigo Vivi <rodrigo.vivi@intel.com> :) Thanks a lot for the patch! merging asap... > --- > drivers/gpu/drm/i915/intel_ddi.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index eff3b51872eb..123a3253453f 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -2098,6 +2098,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder, > if (IS_CANNONLAKE(dev_priv)) { > /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */ > val = I915_READ(DPCLKA_CFGCR0); > + val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); > val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port); > I915_WRITE(DPCLKA_CFGCR0, val); > > -- > 2.15.1 >
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index eff3b51872eb..123a3253453f 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -2098,6 +2098,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder, if (IS_CANNONLAKE(dev_priv)) { /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */ val = I915_READ(DPCLKA_CFGCR0); + val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port); I915_WRITE(DPCLKA_CFGCR0, val);
Without masking out the old value, we can end up pointing the DDI to a disabled PLL, which makes the system fall over. Mask out the previous value before setting the PLL to DDI mapping. This can be observed by running igt/testdisplay with both an eDP and HDMI/DP output active. v2: Add the Bugzilla link Fixes: 555e38d273172 ("drm/i915/cnl: DDI - PLL mapping") Testcase: igt/testdisplay Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103997 Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Matt Atwood <matthew.s.atwood@intel.com> Signed-off-by: James Ausmus <james.ausmus@intel.com> --- drivers/gpu/drm/i915/intel_ddi.c | 1 + 1 file changed, 1 insertion(+)