diff mbox

sdhci: pxav3 controller needs 32 bit ADMA addressing

Message ID 44DD7577-7CB6-42D0-9427-A8731C248612@marvell.com (mailing list archive)
State New, archived
Headers show

Commit Message

Philip Rakity July 11, 2011, 9:47 p.m. UTC
enable the quirk.

Best used in conjunction with patch downgrading
ADMA to SDMA when transfer is not aligned.

Signed-off-by: Philip Rakity <prakity@marvell.com>
---
 drivers/mmc/host/sdhci-pxav3.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

Comments

Zhangfei Gao July 14, 2011, 1:48 a.m. UTC | #1
On Tue, Jul 12, 2011 at 5:47 AM, Philip Rakity <prakity@marvell.com> wrote:
>
> enable the quirk.
>
> Best used in conjunction with patch downgrading
> ADMA to SDMA when transfer is not aligned.
>
> Signed-off-by: Philip Rakity <prakity@marvell.com>
> ---
>  drivers/mmc/host/sdhci-pxav3.c |    3 ++-
>  1 files changed, 2 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
> index 4198dbb..fc7e4a5 100644
> --- a/drivers/mmc/host/sdhci-pxav3.c
> +++ b/drivers/mmc/host/sdhci-pxav3.c
> @@ -195,7 +195,8 @@ static int __devinit sdhci_pxav3_probe(struct platform_device *pdev)
>        clk_enable(clk);
>
>        host->quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
> -               | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
> +               | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
> +               | SDHCI_QUIRK_32BIT_ADMA_SIZE;
>
>        /* enable 1/8V DDR capable */
>        host->mmc->caps |= MMC_CAP_1_8V_DDR;
> --
> 1.7.0.4
>
>

Acked-by:  Zhangfei Gao <zhangfei.gao@marvell.com>
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Chris Ball July 28, 2011, 10:27 p.m. UTC | #2
Hi Philip,

On Mon, Jul 11 2011, Philip Rakity wrote:
> enable the quirk.
>
> Best used in conjunction with patch downgrading
> ADMA to SDMA when transfer is not aligned.
>
> Signed-off-by: Philip Rakity <prakity@marvell.com>
> ---
>  drivers/mmc/host/sdhci-pxav3.c |    3 ++-
>  1 files changed, 2 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
> index 4198dbb..fc7e4a5 100644
> --- a/drivers/mmc/host/sdhci-pxav3.c
> +++ b/drivers/mmc/host/sdhci-pxav3.c
> @@ -195,7 +195,8 @@ static int __devinit sdhci_pxav3_probe(struct platform_device *pdev)
>  	clk_enable(clk);
>  
>  	host->quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
> -		| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
> +		| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
> +		| SDHCI_QUIRK_32BIT_ADMA_SIZE;
>  
>  	/* enable 1/8V DDR capable */
>  	host->mmc->caps |= MMC_CAP_1_8V_DDR;

Pushed to mmc-next for 3.1 with Zhangfei's ACK, thanks.

- Chris.
diff mbox

Patch

diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
index 4198dbb..fc7e4a5 100644
--- a/drivers/mmc/host/sdhci-pxav3.c
+++ b/drivers/mmc/host/sdhci-pxav3.c
@@ -195,7 +195,8 @@  static int __devinit sdhci_pxav3_probe(struct platform_device *pdev)
 	clk_enable(clk);
 
 	host->quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
-		| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
+		| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
+		| SDHCI_QUIRK_32BIT_ADMA_SIZE;
 
 	/* enable 1/8V DDR capable */
 	host->mmc->caps |= MMC_CAP_1_8V_DDR;