diff mbox

[v5,2/4] clk: meson-axg: add clocks dt-bindings required header

Message ID 20171207095300.15384-3-yixun.lan@amlogic.com (mailing list archive)
State Superseded, archived
Headers show

Commit Message

Yixun Lan Dec. 7, 2017, 9:52 a.m. UTC
From: Qiufang Dai <qiufang.dai@amlogic.com>

Add the required header for the clocks ID dt-bindings
exported from various subsystem in the Meson-AXG SoC.

Signed-off-by: Qiufang Dai <qiufang.dai@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
 include/dt-bindings/clock/axg-clkc.h | 71 ++++++++++++++++++++++++++++++++++++
 1 file changed, 71 insertions(+)
 create mode 100644 include/dt-bindings/clock/axg-clkc.h

Comments

Rob Herring Dec. 7, 2017, 10:10 p.m. UTC | #1
On Thu, Dec 07, 2017 at 05:52:58PM +0800, Yixun Lan wrote:
> From: Qiufang Dai <qiufang.dai@amlogic.com>
> 
> Add the required header for the clocks ID dt-bindings
> exported from various subsystem in the Meson-AXG SoC.
> 
> Signed-off-by: Qiufang Dai <qiufang.dai@amlogic.com>
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> ---
>  include/dt-bindings/clock/axg-clkc.h | 71 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 71 insertions(+)
>  create mode 100644 include/dt-bindings/clock/axg-clkc.h

Please add acks when posting new versions.

Rob
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Yixun Lan Dec. 8, 2017, 1:14 a.m. UTC | #2
On 12/08/17 06:10, Rob Herring wrote:
> On Thu, Dec 07, 2017 at 05:52:58PM +0800, Yixun Lan wrote:
>> From: Qiufang Dai <qiufang.dai@amlogic.com>
>>
>> Add the required header for the clocks ID dt-bindings
>> exported from various subsystem in the Meson-AXG SoC.
>>
>> Signed-off-by: Qiufang Dai <qiufang.dai@amlogic.com>
>> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
>> ---
>>  include/dt-bindings/clock/axg-clkc.h | 71 ++++++++++++++++++++++++++++++++++++
>>  1 file changed, 71 insertions(+)
>>  create mode 100644 include/dt-bindings/clock/axg-clkc.h
> 
> Please add acks when posting new versions.
> 

HI Rob
 thanks for the suggestion, I will keep this in mind
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Jerome Brunet Dec. 8, 2017, 9:33 a.m. UTC | #3
On Thu, 2017-12-07 at 16:10 -0600, Rob Herring wrote:
> On Thu, Dec 07, 2017 at 05:52:58PM +0800, Yixun Lan wrote:
> > From: Qiufang Dai <qiufang.dai@amlogic.com>
> > 
> > Add the required header for the clocks ID dt-bindings
> > exported from various subsystem in the Meson-AXG SoC.
> > 
> > Signed-off-by: Qiufang Dai <qiufang.dai@amlogic.com>
> > Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> > ---
> >  include/dt-bindings/clock/axg-clkc.h | 71
> > ++++++++++++++++++++++++++++++++++++
> >  1 file changed, 71 insertions(+)
> >  create mode 100644 include/dt-bindings/clock/axg-clkc.h
> 
> Please add acks when posting new versions.
> 
> Rob

Yixun, please be consistent about this. Maintainers are not going to dig
through your previous revision to collect Tags

I believe Neil acked patch 3, didn't he ?

Please resend your series with the Tags collected
If not already done, please make sure patches 1-3 apply on top of rc1 and patch
4 on Kevin's dt64 branch.

Thanks
Jerome

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Yixun Lan Dec. 8, 2017, 2:22 p.m. UTC | #4
On 12/08/17 17:33, Jerome Brunet wrote:
> On Thu, 2017-12-07 at 16:10 -0600, Rob Herring wrote:
>> On Thu, Dec 07, 2017 at 05:52:58PM +0800, Yixun Lan wrote:
>>> From: Qiufang Dai <qiufang.dai@amlogic.com>
>>>
>>> Add the required header for the clocks ID dt-bindings
>>> exported from various subsystem in the Meson-AXG SoC.
>>>
>>> Signed-off-by: Qiufang Dai <qiufang.dai@amlogic.com>
>>> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
>>> ---
>>>  include/dt-bindings/clock/axg-clkc.h | 71
>>> ++++++++++++++++++++++++++++++++++++
>>>  1 file changed, 71 insertions(+)
>>>  create mode 100644 include/dt-bindings/clock/axg-clkc.h
>>
>> Please add acks when posting new versions.
>>
>> Rob
> 
> Yixun, please be consistent about this. Maintainers are not going to dig
> through your previous revision to collect Tags
> 
> I believe Neil acked patch 3, didn't he ?
> 
> Please resend your series with the Tags collected
sorry, I missed Neil's ACK for the pacth [3/4]

let's just wait for a few more days, to see if there are more comments
coming up, then I would fold them together

> If not already done, please make sure patches 1-3 apply on top of rc1 and patch
> 4 on Kevin's dt64 branch.
> 
the above is already base on -rc2, and patch 4 can apply to kevin's dt64
cleanly

> Thanks
> Jerome
> 
> .
> 




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Jerome Brunet Dec. 8, 2017, 2:27 p.m. UTC | #5
On Fri, 2017-12-08 at 22:22 +0800, Yixun Lan wrote:
> let's just wait for a few more days, to see if there are more comments
> coming up, then I would fold them together

That's up to you. Keep in mind that rc4 is coming up and I'll need some time
to test/verify the final version 
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diff mbox

Patch

diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h
new file mode 100644
index 000000000000..941ac70e7f30
--- /dev/null
+++ b/include/dt-bindings/clock/axg-clkc.h
@@ -0,0 +1,71 @@ 
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Meson-AXG clock tree IDs
+ *
+ * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __AXG_CLKC_H
+#define __AXG_CLKC_H
+
+#define CLKID_SYS_PLL				0
+#define CLKID_FIXED_PLL				1
+#define CLKID_FCLK_DIV2				2
+#define CLKID_FCLK_DIV3				3
+#define CLKID_FCLK_DIV4				4
+#define CLKID_FCLK_DIV5				5
+#define CLKID_FCLK_DIV7				6
+#define CLKID_GP0_PLL				7
+#define CLKID_CLK81				10
+#define CLKID_MPLL0				11
+#define CLKID_MPLL1				12
+#define CLKID_MPLL2				13
+#define CLKID_MPLL3				14
+#define CLKID_DDR				15
+#define CLKID_AUDIO_LOCKER			16
+#define CLKID_MIPI_DSI_HOST			17
+#define CLKID_ISA				18
+#define CLKID_PL301				19
+#define CLKID_PERIPHS				20
+#define CLKID_SPICC0				21
+#define CLKID_I2C				22
+#define CLKID_RNG0				23
+#define CLKID_UART0				24
+#define CLKID_MIPI_DSI_PHY			25
+#define CLKID_SPICC1				26
+#define CLKID_PCIE_A				27
+#define CLKID_PCIE_B				28
+#define CLKID_HIU_IFACE				29
+#define CLKID_ASSIST_MISC			30
+#define CLKID_SD_EMMC_B				31
+#define CLKID_SD_EMMC_C				32
+#define CLKID_DMA				33
+#define CLKID_SPI				34
+#define CLKID_AUDIO				35
+#define CLKID_ETH				36
+#define CLKID_UART1				37
+#define CLKID_G2D				38
+#define CLKID_USB0				39
+#define CLKID_USB1				40
+#define CLKID_RESET				41
+#define CLKID_USB				42
+#define CLKID_AHB_ARB0				43
+#define CLKID_EFUSE				44
+#define CLKID_BOOT_ROM				45
+#define CLKID_AHB_DATA_BUS			46
+#define CLKID_AHB_CTRL_BUS			47
+#define CLKID_USB1_DDR_BRIDGE			48
+#define CLKID_USB0_DDR_BRIDGE			49
+#define CLKID_MMC_PCLK				50
+#define CLKID_VPU_INTR				51
+#define CLKID_SEC_AHB_AHB3_BRIDGE		52
+#define CLKID_GIC				53
+#define CLKID_AO_MEDIA_CPU			54
+#define CLKID_AO_AHB_SRAM			55
+#define CLKID_AO_AHB_BUS			56
+#define CLKID_AO_IFACE				57
+#define CLKID_AO_I2C				58
+#define CLKID_SD_EMMC_B_CLK0			59
+#define CLKID_SD_EMMC_C_CLK0			60
+
+#endif /* __AXG_CLKC_H */