| Message ID | 20171206153005.6144-2-stefan@agner.ch (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, Dec 6, 2017 at 1:29 PM, Stefan Agner <stefan@agner.ch> wrote: > The Colibri pins PWM<A> and <D> are multiplexed on the module, make > sure the secondary SoC pin is not active. > > Signed-off-by: Stefan Agner <stefan@agner.ch> I haven't really understood the commit message, but this is probably because I don't have access to the schematics. Anyway: Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
On 2017-12-16 15:01, Fabio Estevam wrote: > On Wed, Dec 6, 2017 at 1:29 PM, Stefan Agner <stefan@agner.ch> wrote: >> The Colibri pins PWM<A> and <D> are multiplexed on the module, make >> sure the secondary SoC pin is not active. >> >> Signed-off-by: Stefan Agner <stefan@agner.ch> > > I haven't really understood the commit message, but this is probably > because I don't have access to the schematics. It means that the modules pins are connected to two SoC pads. It is also mentioned in the Colibri iMX7 datasheet. This allows to use the module pin for a different purpose, but we mux it such that it is usable for the primary purpose (which is PWM). > > Anyway: > > Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Thanks! -- Stefan
diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi index 60ea7557d8c9..dae6b561145b 100644 --- a/arch/arm/boot/dts/imx7-colibri.dtsi +++ b/arch/arm/boot/dts/imx7-colibri.dtsi @@ -507,6 +507,7 @@ pinctrl_pwm1: pwm1-grp { fsl,pins = < MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x79 + MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x4 >; }; @@ -525,6 +526,7 @@ pinctrl_pwm4: pwm4-grp { fsl,pins = < MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x79 + MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x4 >; };
The Colibri pins PWM<A> and <D> are multiplexed on the module, make sure the secondary SoC pin is not active. Signed-off-by: Stefan Agner <stefan@agner.ch> --- arch/arm/boot/dts/imx7-colibri.dtsi | 2 ++ 1 file changed, 2 insertions(+)