| Message ID | 20171216001117.14232-1-rafael.antognolli@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Sat, Dec 16, 2017 at 12:11:16AM +0000, Rafael Antognolli wrote: > This workaround supposedly fixes some hangs in the VF unit. > > Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> > Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Both patches merged to dinq. Thanks for patches and reviews. > --- > drivers/gpu/drm/i915/i915_reg.h | 3 +++ > drivers/gpu/drm/i915/intel_pm.c | 5 +++++ > 2 files changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 09bf043c1c2e..a9a6d6698bb1 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3875,6 +3875,9 @@ enum { > #define SARBUNIT_CLKGATE_DIS (1 << 5) > #define RCCUNIT_CLKGATE_DIS (1 << 7) > > +#define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434) > +#define VFUNIT_CLKGATE_DIS (1 << 20) > + > /* > * Display engine regs > */ > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index a349c4fd51ff..e33842d6bb14 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -8448,6 +8448,11 @@ static void cnl_init_clock_gating(struct drm_i915_private *dev_priv) > if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0)) > val |= SARBUNIT_CLKGATE_DIS; > I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, val); > + > + /* WaDisableVFclkgate:cnl */ > + val = I915_READ(UNSLICE_UNIT_LEVEL_CLKGATE); > + val |= VFUNIT_CLKGATE_DIS; > + I915_WRITE(UNSLICE_UNIT_LEVEL_CLKGATE, val); > } > > static void cfl_init_clock_gating(struct drm_i915_private *dev_priv) > -- > 2.14.3 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 09bf043c1c2e..a9a6d6698bb1 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3875,6 +3875,9 @@ enum { #define SARBUNIT_CLKGATE_DIS (1 << 5) #define RCCUNIT_CLKGATE_DIS (1 << 7) +#define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434) +#define VFUNIT_CLKGATE_DIS (1 << 20) + /* * Display engine regs */ diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index a349c4fd51ff..e33842d6bb14 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -8448,6 +8448,11 @@ static void cnl_init_clock_gating(struct drm_i915_private *dev_priv) if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0)) val |= SARBUNIT_CLKGATE_DIS; I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, val); + + /* WaDisableVFclkgate:cnl */ + val = I915_READ(UNSLICE_UNIT_LEVEL_CLKGATE); + val |= VFUNIT_CLKGATE_DIS; + I915_WRITE(UNSLICE_UNIT_LEVEL_CLKGATE, val); } static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)