| Message ID | 1513698900-10638-11-git-send-email-sricharan@codeaurora.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Dec 19, 2017 at 09:24:55PM +0530, Sricharan R wrote: > From: Stephen Boyd <sboyd@codeaurora.org> > > The ACC and GCC regions present in KPSSv1 contain registers to > control clocks and power to each Krait CPU and L2. Documenting > the bindings here. > > Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> > --- > .../devicetree/bindings/arm/msm/qcom,kpss-acc.txt | 7 +++++ > .../devicetree/bindings/arm/msm/qcom,kpss-gcc.txt | 32 ++++++++++++++++++++++ > 2 files changed, 39 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt Reviewed-by: Rob Herring <robh@kernel.org>
On 12/21/2017 2:43 AM, Rob Herring wrote: > On Tue, Dec 19, 2017 at 09:24:55PM +0530, Sricharan R wrote: >> From: Stephen Boyd <sboyd@codeaurora.org> >> >> The ACC and GCC regions present in KPSSv1 contain registers to >> control clocks and power to each Krait CPU and L2. Documenting >> the bindings here. >> >> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> >> --- >> .../devicetree/bindings/arm/msm/qcom,kpss-acc.txt | 7 +++++ >> .../devicetree/bindings/arm/msm/qcom,kpss-gcc.txt | 32 ++++++++++++++++++++++ >> 2 files changed, 39 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt > > Reviewed-by: Rob Herring <robh@kernel.org> Thanks !! Regards, Sricharan
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt index 1333db9..382a574 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt +++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt @@ -21,10 +21,17 @@ PROPERTIES the register region. An optional second element specifies the base address and size of the alias register region. +- clock-output-names: + Usage: optional + Value type: <string> + Definition: Name of the output clock. Typically acpuX_aux where X is a + CPU number starting at 0. + Example: clock-controller@2088000 { compatible = "qcom,kpss-acc-v2"; reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + clock-output-names = "acpu0_aux"; }; diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt new file mode 100644 index 0000000..37fc0a4 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt @@ -0,0 +1,32 @@ +Krait Processor Sub-system (KPSS) Global Clock Controller (GCC) + +PROPERTIES + +- compatible: + Usage: required + Value type: <string> + Definition: should be one of the following. The generic compatible + "qcom,kpss-gcc" should also be included. + "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc" + "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc" + "qcom,kpss-gcc-msm8974", "qcom,kpss-gcc" + "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc" + +- reg: + Usage: required + Value type: <prop-encoded-array> + Definition: base address and size of the register region + +- clock-output-names: + Usage: required + Value type: <string> + Definition: Name of the output clock. Typically acpu_l2_aux indicating + an L2 cache auxiliary clock. + +Example: + + l2cc: clock-controller@2011000 { + compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc"; + reg = <0x2011000 0x1000>; + clock-output-names = "acpu_l2_aux"; + };