| Message ID | 20171230113043.30237-2-icenowy@aosc.io (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Sat, Dec 30, 2017 at 7:30 PM, Icenowy Zheng <icenowy@aosc.io> wrote: > The H3/H5 SoCs have a HDMI output and a TV Composite output. > > Add simplefb nodes for these outputs. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > --- > Changes in v4: > - Dropped extra clocks (bus clocks and HDMI DDC clocks), only keep the > clocks that are needed to display framebuffer to the monitor. Looks good. I assume you've tested this? It does continue to work with the bus and DDC clocks disabled, right? Thanks ChenYu
在 2018年1月2日星期二 CST 下午4:11:04，Chen-Yu Tsai 写道： > On Sat, Dec 30, 2017 at 7:30 PM, Icenowy Zheng <icenowy@aosc.io> wrote: > > The H3/H5 SoCs have a HDMI output and a TV Composite output. > > > > Add simplefb nodes for these outputs. > > > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > > --- > > Changes in v4: > > - Dropped extra clocks (bus clocks and HDMI DDC clocks), only keep the > > > > clocks that are needed to display framebuffer to the monitor. > > Looks good. I assume you've tested this? It does continue to work > with the bus and DDC clocks disabled, right? Yes. This patchset is tested in Orange Pi PC and SoPine w/ Baseboard "Model A". > > Thanks > ChenYu
Hi, Dne torek, 02. januar 2018 ob 09:14:37 CET je Icenowy Zheng napisal(a): > 在 2018年1月2日星期二 CST 下午4:11:04，Chen-Yu Tsai 写道： > > > On Sat, Dec 30, 2017 at 7:30 PM, Icenowy Zheng <icenowy@aosc.io> wrote: > > > The H3/H5 SoCs have a HDMI output and a TV Composite output. > > > > > > Add simplefb nodes for these outputs. > > > > > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > > > --- > > > Changes in v4: > > > - Dropped extra clocks (bus clocks and HDMI DDC clocks), only keep the > > > > > > clocks that are needed to display framebuffer to the monitor. > > > > Looks good. I assume you've tested this? It does continue to work > > with the bus and DDC clocks disabled, right? > > Yes. This patchset is tested in Orange Pi PC and SoPine w/ Baseboard "Model > A". I think DDC clock is misnamed and according to DW HDMI binding should be named ISFR (clock for special function registers). I did few test tests when writing U-Boot driver and it has to be enabled all the time for driver to work correctly. I did few additional tests few days back - if only DDC clock is enabled and PLL video/HDMI clock disabled, DW HDMI registers are accessible. I guess DDC clock in your case is not needed because controller is already configured correctly. Best regards, Jernej
On Tue, Jan 2, 2018 at 4:14 PM, Icenowy Zheng <icenowy@aosc.io> wrote: > 在 2018年1月2日星期二 CST 下午4:11:04，Chen-Yu Tsai 写道： >> On Sat, Dec 30, 2017 at 7:30 PM, Icenowy Zheng <icenowy@aosc.io> wrote: >> > The H3/H5 SoCs have a HDMI output and a TV Composite output. >> > >> > Add simplefb nodes for these outputs. >> > >> > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> >> > --- >> > Changes in v4: >> > - Dropped extra clocks (bus clocks and HDMI DDC clocks), only keep the >> > >> > clocks that are needed to display framebuffer to the monitor. >> >> Looks good. I assume you've tested this? It does continue to work >> with the bus and DDC clocks disabled, right? > > Yes. This patchset is tested in Orange Pi PC and SoPine w/ Baseboard "Model > A". Applied this one. ChenYu
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index fcb909658cf0..7a83b15225c7 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -53,6 +53,30 @@ #address-cells = <1>; #size-cells = <1>; + chosen { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + framebuffer-hdmi { + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; + allwinner,pipeline = "mixer0-lcd0-hdmi"; + clocks = <&display_clocks CLK_MIXER0>, + <&ccu CLK_TCON0>, <&ccu CLK_HDMI>; + status = "disabled"; + }; + + framebuffer-tve { + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; + allwinner,pipeline = "mixer1-lcd1-tve"; + clocks = <&display_clocks CLK_MIXER1>, + <&ccu CLK_TVE>; + status = "disabled"; + }; + }; + clocks { #address-cells = <1>; #size-cells = <1>;
The H3/H5 SoCs have a HDMI output and a TV Composite output. Add simplefb nodes for these outputs. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> --- Changes in v4: - Dropped extra clocks (bus clocks and HDMI DDC clocks), only keep the clocks that are needed to display framebuffer to the monitor. arch/arm/boot/dts/sunxi-h3-h5.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)