Message ID | 20180106001044.108163-3-yixun.lan@amlogic.com (mailing list archive) |
---|---|
State | Superseded |
Headers | show |
On Sat, 2018-01-06 at 08:10 +0800, Yixun Lan wrote: > When update the clock info for the UART controller in the EE domain, > the driver explicitly require 'pclk' in order to work properly. > > With current logic of the code, the driver will go for the legacy clock probe > routine[1] if it find current compatible string match to 'amlogic,meson-uart', > which result in not requesting the 'pclk' clock, thus break the driver in the end. > > [1] drivers/tty/serial/meson_uart.c:685 > > /* Use legacy way until all platforms switch to new bindings */ > if (of_device_is_compatible(pdev->dev.of_node, "amlogic,meson-uart")) > ret = meson_uart_probe_clocks_legacy(pdev, port); > else > ret = meson_uart_probe_clocks(pdev, port); I don't think you should add this code snip here. Anybody can look at the driver code to see that > > Acked-by: Jerome Brunet <jbrunet@baylibre.com> > Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 70c776ef7aa7..644d0f9eaf8c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -164,17 +164,21 @@ }; uart_A: serial@24000 { - compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart"; + compatible = "amlogic,meson-gx-uart"; reg = <0x0 0x24000 0x0 0x18>; interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; status = "disabled"; + clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; }; uart_B: serial@23000 { - compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart"; + compatible = "amlogic,meson-gx-uart"; reg = <0x0 0x23000 0x0 0x18>; interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; status = "disabled"; + clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; }; };