| Message ID | 1515489651-13488-1-git-send-email-Anson.Huang@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Jan 09, 2018 at 05:20:51PM +0800, Anson Huang wrote: > Add i.MX7 SNVS RTC clock. > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> > --- > changes since v2: > improve the binding doc statement about clocks. > Documentation/devicetree/bindings/crypto/fsl-sec4.txt | 15 +++++++++++++++ > arch/arm/boot/dts/imx7s.dtsi | 2 ++ > 2 files changed, 17 insertions(+) > > diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt > index 76aec8a..7329f29 100644 > --- a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt > +++ b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt > @@ -415,12 +415,25 @@ Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node > value type: <u32> > Definition: LP register offset. default it is 0x34. > > + - clocks > + Usage: required if SNVS LP RTC requires explicit enablement of clocks > + Value type: <prop_encoded-array> > + Definition: a clock specifier describing the clock required for > + enabling and disabling SNVS LP RTC. > + This clock seem optional. Should we indicate it here explicitly? BTW, i thought we probably could update poweroff and key as well at the same time since device tree changes can go separately. Does it make sense? Regards Dong Aisheng > + - clock-names > + Usage: required if SNVS LP RTC requires explicit enablement of clocks > + Value type: <string> > + Definition: clock name string should be "snvs-rtc". > + > EXAMPLE > sec_mon_rtc_lp@1 { > compatible = "fsl,sec-v4.0-mon-rtc-lp"; > interrupts = <93 2>; > regmap = <&snvs>; > offset = <0x34>; > + clocks = <&clks IMX7D_SNVS_CLK>; > + clock-names = "snvs-rtc"; > }; > > ===================================================================== > @@ -543,6 +556,8 @@ FULL EXAMPLE > regmap = <&sec_mon>; > offset = <0x34>; > interrupts = <93 2>; > + clocks = <&clks IMX7D_SNVS_CLK>; > + clock-names = "snvs-rtc"; > }; > > snvs-pwrkey@020cc000 { > diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi > index 9aa2bb9..02baf42 100644 > --- a/arch/arm/boot/dts/imx7s.dtsi > +++ b/arch/arm/boot/dts/imx7s.dtsi > @@ -551,6 +551,8 @@ > offset = <0x34>; > interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX7D_SNVS_CLK>; > + clock-names = "snvs-rtc"; > }; > > snvs_poweroff: snvs-poweroff { > -- > 1.9.1 >
Best Regards! Anson Huang > -----Original Message----- > From: Dong Aisheng [mailto:dongas86@gmail.com] > Sent: 2018-01-09 5:47 PM > To: Anson Huang <anson.huang@nxp.com> > Cc: Horia Geantă <horia.geanta@nxp.com>; Aymen Sghaier > <aymen.sghaier@nxp.com>; herbert@gondor.apana.org.au; > davem@davemloft.net; robh+dt@kernel.org; mark.rutland@arm.com; > shawnguo@kernel.org; kernel@pengutronix.de; Fabio Estevam > <fabio.estevam@nxp.com>; linux@armlinux.org.uk; > mturquette@baylibre.com; sboyd@codeaurora.org; Adriana Reus > <adriana.reus@nxp.com>; stefan@agner.ch; linux-crypto@vger.kernel.org; > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm- > kernel@lists.infradead.org; linux-clk@vger.kernel.org; dl-linux-imx <linux- > imx@nxp.com> > Subject: Re: [PATCH V3 2/2] ARM: dts: imx7s: add snvs rtc clock > > On Tue, Jan 09, 2018 at 05:20:51PM +0800, Anson Huang wrote: > > Add i.MX7 SNVS RTC clock. > > > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> > > --- > > changes since v2: > > improve the binding doc statement about clocks. > > Documentation/devicetree/bindings/crypto/fsl-sec4.txt | 15 > +++++++++++++++ > > arch/arm/boot/dts/imx7s.dtsi | 2 ++ > > 2 files changed, 17 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt > > b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt > > index 76aec8a..7329f29 100644 > > --- a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt > > +++ b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt > > @@ -415,12 +415,25 @@ Secure Non-Volatile Storage (SNVS) Low Power (LP) > RTC Node > > value type: <u32> > > Definition: LP register offset. default it is 0x34. > > > > + - clocks > > + Usage: required if SNVS LP RTC requires explicit enablement of clocks > > + Value type: <prop_encoded-array> > > + Definition: a clock specifier describing the clock required for > > + enabling and disabling SNVS LP RTC. > > + > > This clock seem optional. > Should we indicate it here explicitly? Will add a optional in usage. > > BTW, i thought we probably could update poweroff and key as well at the same > time since device tree changes can go separately. > Does it make sense? I think this patch set is only for RTC case since snvs-rtc driver already handle the clock. But for poweroff and powerkey, their drivers are NOT handling clocks currently, we can add them when driver ready to handle clocks. Should be in another patch set later. Anson. > > Regards > Dong Aisheng > > > + - clock-names > > + Usage: required if SNVS LP RTC requires explicit enablement of clocks > > + Value type: <string> > > + Definition: clock name string should be "snvs-rtc". > > + > > EXAMPLE > > sec_mon_rtc_lp@1 { > > compatible = "fsl,sec-v4.0-mon-rtc-lp"; > > interrupts = <93 2>; > > regmap = <&snvs>; > > offset = <0x34>; > > + clocks = <&clks IMX7D_SNVS_CLK>; > > + clock-names = "snvs-rtc"; > > }; > > > > > ============================================================ > ========= > > @@ -543,6 +556,8 @@ FULL EXAMPLE > > regmap = <&sec_mon>; > > offset = <0x34>; > > interrupts = <93 2>; > > + clocks = <&clks IMX7D_SNVS_CLK>; > > + clock-names = "snvs-rtc"; > > }; > > > > snvs-pwrkey@020cc000 { > > diff --git a/arch/arm/boot/dts/imx7s.dtsi > > b/arch/arm/boot/dts/imx7s.dtsi index 9aa2bb9..02baf42 100644 > > --- a/arch/arm/boot/dts/imx7s.dtsi > > +++ b/arch/arm/boot/dts/imx7s.dtsi > > @@ -551,6 +551,8 @@ > > offset = <0x34>; > > interrupts = <GIC_SPI 19 > IRQ_TYPE_LEVEL_HIGH>, > > <GIC_SPI 20 > IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&clks IMX7D_SNVS_CLK>; > > + clock-names = "snvs-rtc"; > > }; > > > > snvs_poweroff: snvs-poweroff { > > -- > > 1.9.1 > >
Best Regards! Anson Huang > -----Original Message----- > From: Dong Aisheng [mailto:dongas86@gmail.com] > Sent: 2018-01-09 5:44 PM > To: Anson Huang <anson.huang@nxp.com> > Cc: Horia Geantă <horia.geanta@nxp.com>; Aymen Sghaier > <aymen.sghaier@nxp.com>; herbert@gondor.apana.org.au; > davem@davemloft.net; robh+dt@kernel.org; mark.rutland@arm.com; > shawnguo@kernel.org; kernel@pengutronix.de; Fabio Estevam > <fabio.estevam@nxp.com>; linux@armlinux.org.uk; > mturquette@baylibre.com; sboyd@codeaurora.org; Adriana Reus > <adriana.reus@nxp.com>; stefan@agner.ch; linux-crypto@vger.kernel.org; > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm- > kernel@lists.infradead.org; linux-clk@vger.kernel.org; dl-linux-imx <linux- > imx@nxp.com> > Subject: Re: [PATCH V3 1/2] clk: imx: imx7d: add the snvs clock > > On Tue, Jan 09, 2018 at 05:20:50PM +0800, Anson Huang wrote: > > According to the i.MX7D Reference Manual, SNVS block has a clock gate, > > accessing SNVS block would need this clock gate to be enabled, add it > > into clock tree so that SNVS module driver can operate this clock > > gate. > > > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> > > You missed the last round review tags. > > Regards > Dong Aisheng Thanks for reminder, already sent out a V4 patch set to add tags. Anson.
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c index 80dc211..f34f1ec 100644 --- a/drivers/clk/imx/clk-imx7d.c +++ b/drivers/clk/imx/clk-imx7d.c @@ -795,6 +795,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) clks[IMX7D_DRAM_PHYM_ALT_ROOT_CLK] = imx_clk_gate4("dram_phym_alt_root_clk", "dram_phym_alt_post_div", base + 0x4130, 0); clks[IMX7D_DRAM_ALT_ROOT_CLK] = imx_clk_gate4("dram_alt_root_clk", "dram_alt_post_div", base + 0x4130, 0); clks[IMX7D_OCOTP_CLK] = imx_clk_gate4("ocotp_clk", "ipg_root_clk", base + 0x4230, 0); + clks[IMX7D_SNVS_CLK] = imx_clk_gate4("snvs_clk", "ipg_root_clk", base + 0x4250, 0); clks[IMX7D_USB_HSIC_ROOT_CLK] = imx_clk_gate4("usb_hsic_root_clk", "usb_hsic_post_div", base + 0x4420, 0); clks[IMX7D_SDMA_CORE_CLK] = imx_clk_gate4("sdma_root_clk", "ahb_root_clk", base + 0x4480, 0); clks[IMX7D_PCIE_CTRL_ROOT_CLK] = imx_clk_gate4("pcie_ctrl_root_clk", "pcie_ctrl_post_div", base + 0x4600, 0); diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h index e2f99ae..dc51904 100644 --- a/include/dt-bindings/clock/imx7d-clock.h +++ b/include/dt-bindings/clock/imx7d-clock.h @@ -452,5 +452,6 @@ #define IMX7D_OCOTP_CLK 439 #define IMX7D_NAND_RAWNAND_CLK 440 #define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 441 -#define IMX7D_CLK_END 442 +#define IMX7D_SNVS_CLK 442 +#define IMX7D_CLK_END 443 #endif /* __DT_BINDINGS_CLOCK_IMX7D_H */
According to the i.MX7D Reference Manual, SNVS block has a clock gate, accessing SNVS block would need this clock gate to be enabled, add it into clock tree so that SNVS module driver can operate this clock gate. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> --- drivers/clk/imx/clk-imx7d.c | 1 + include/dt-bindings/clock/imx7d-clock.h | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-)